 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MB86294/294S Graphics Controller Specifications Revision 1.0 31st Jan, 2003 Copyright (c) FUJITSU LIMITED 2001 ALL RIGHTS RESERVED * The specifications in this manual are subject to change without notice. Department before purchasing the product described in this manual. Contact our Sales * Information and circuit diagrams in this manual are only examples of device applications, they are not intended to be used in actual equipment. Also, Fujitsu accepts no responsibility for infringement of patents or other rights owned by third parties caused by use of the information and circuit diagrams. * The contents of this manual must not be reprinted or duplicated without permission of Fujitsu. * Fujitsu's semiconductor devices are intended for standard uses (such as office equipment (computers and OA equipment), industrial/communications/measuring equipment, and personal/home equipment). Customers using semiconductor devices for special applications (including aerospace, nuclear, military and medical applications) in which a failure or malfunction might endanger life or limb and which require extremely high reliability must contact our Sales Department first. If damage is caused by such use of our semiconductor devices without first consulting our Sales Department, Fujitsu will not assume any responsibility for the loss. * Semiconductor devices fail with a known probability. Customers must use safety design (such as redundant design, fireproof design, over-current prevention design, and malfunction prevention design) so that failures will not cause accidents, injury or death). * If the products described in this manual fall within the goods or technologies regulated by the Foreign Exchange and Foreign Trade Law, permission must be obtained before exporting the goods or technologies. ii Update history Date 2003.1.31 Version 1.0 Page count 303 First release Change CONTENTS 1 GENERAL ............................................................................................................................ 11 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.9 2 PREFACE ..................................................................................................................... 11 FEATURES .................................................................................................................... 12 BLOCK DIAGRAM........................................................................................................... 13 FUNCTIONAL OVERVIEW ................................................................................................. 14 Host CPU interface................................................................................................. 14 External memory interface ..................................................................................... 16 Display controller ................................................................................................... 17 Video Capture......................................................................................................... 19 Geometry processing............................................................................................... 19 2D Drawing ............................................................................................................ 20 3D Drawing ............................................................................................................ 22 Special effects ......................................................................................................... 23 Others .................................................................................................................... 26 PINS .................................................................................................................................... 27 2.1 2.1.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 SIGNALS ...................................................................................................................... 27 Signal lines............................................................................................................. 27 PIN ASSIGNMENT .......................................................................................................... 28 PBGA256 Pin assignment diagram (TOP_VIEW).................................................... 28 PBGA256 Pin assignment table .............................................................................. 29 HQFP256 Pin assignment diagram ......................................................................... 30 HQFP256 Pin assignment table.............................................................................. 31 PIN FUNCTION .............................................................................................................. 33 Host CPU interface................................................................................................. 33 Video output interface............................................................................................. 35 Video Capture interface.......................................................................................... 36 Graphics memory interface..................................................................................... 37 Clock input ............................................................................................................. 38 Test pins................................................................................................................. 39 Reset sequence ....................................................................................................... 39 3 PROCEDURE OF THE HARDWARE INITIALIZATION ........................................................... 40 3.1 3.2 3.3 HARDWARE RESET ......................................................................................................... 40 RE-RESET .................................................................................................................... 40 SOFTWARE RESET ......................................................................................................... 40 4 HOST INTERFACE ............................................................................................................... 41 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4 4.5 4.6 4.7 4.8 5 OPERATION MODE......................................................................................................... 41 Host CPU mode ...................................................................................................... 41 Ready signal mode.................................................................................................. 41 BS signal mode....................................................................................................... 42 Endian.................................................................................................................... 42 ACCESS MODE ............................................................................................................. 43 SRAM interface...................................................................................................... 43 FIFO interface (fixed transfer destination address)................................................. 43 DMA TRANSFER ........................................................................................................... 44 Data transfer unit................................................................................................... 44 Address mode ......................................................................................................... 44 Bus mode................................................................................................................ 45 DMA transfer request ............................................................................................. 45 Ending DMA transfer ............................................................................................. 45 TRANSFER OF LOCAL DISPLAY LIST.................................................................................. 46 INTERRUPT................................................................................................................... 47 SH3 MODE .................................................................................................................. 47 WAIT ........................................................................................................................... 47 MEMORY MAP............................................................................................................... 48 GRAPHICS MEMORY........................................................................................................... 50 5.1 5.1.1 5.1.2 5.1.3 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.4 5.4.1 CONFIGURATION ........................................................................................................... 50 Data type................................................................................................................ 50 Memory Mapping.................................................................................................... 51 Data Format ........................................................................................................... 51 FRAME MANAGEMENT.................................................................................................... 53 Single Buffer .......................................................................................................... 53 Double Buffer ......................................................................................................... 53 MEMORY ACCESS ......................................................................................................... 53 Memory Access by host CPU ................................................................................... 53 Priority of memory accessing .................................................................................. 53 CONNECTION WITH MEMORY ........................................................................................... 54 Connection with memory ........................................................................................ 54 6 DISPLAY CONTROLLER...................................................................................................... 55 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 OVERVIEW ................................................................................................................... 55 DISPLAY FUNCTION........................................................................................................ 55 Layer configuration ................................................................................................ 55 Overlay................................................................................................................... 57 Display parameters ................................................................................................ 59 Display position control .......................................................................................... 60 6.3 6.4 6.4.1 6.4.2 6.5 6.5.1 6.5.2 6.6 6.7 7 DISPLAY COLOR ............................................................................................................ 62 CURSOR ...................................................................................................................... 63 Cursor display function ........................................................................................... 63 Cursor control......................................................................................................... 63 DISPLAY SCAN CONTROL................................................................................................ 64 Applicable display................................................................................................... 64 Interlace display ..................................................................................................... 65 THE EXTERNAL SYNCHRONOUS SIGNAL ............................................................................. 66 VIDEO INTERFACE, NTSC/PAL OUTPUT ........................................................................... 69 VIDEO CAPTURE................................................................................................................. 70 7.1 7.1.1 7.1.2 7.1.3 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 7.3.1 7.3.2 7.4 7.4.1 FORMAT....................................................................................................................... 70 Input Data Format ................................................................................................. 70 Video Signal Capture.............................................................................................. 70 Non-interlace Transformation ................................................................................. 70 VIDEO B UFFER.............................................................................................................. 71 Data Format ........................................................................................................... 71 Synchronous Control .............................................................................................. 71 Area Allocation ....................................................................................................... 71 Window Display...................................................................................................... 72 Interlace Display .................................................................................................... 72 SCALING...................................................................................................................... 73 Video Reduction Function ....................................................................................... 73 Vertical Interpolation .............................................................................................. 73 ERROR HANDLING ......................................................................................................... 73 Error Detection Function ........................................................................................ 73 8 GEOMETRY ENGINE ........................................................................................................... 74 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.2 8.2.1 8.3 8.3.1 8.4 8.4.1 GEOMETRY PIPELINE ..................................................................................................... 74 Processing flow ....................................................................................................... 74 Model-view-projection (MVP) transformation (OC CC coordinate transformation) 75 3D-2D transformation (CC NDC coordinate transformation) ................................ 75 View port transformation (NDC DC coordinate transformation) ........................... 76 View volume clipping.............................................................................................. 76 Back face curling .................................................................................................... 78 DATA FORMAT............................................................................................................... 79 Data format............................................................................................................ 79 SETUP E NGINE ............................................................................................................. 80 Setup processing ..................................................................................................... 80 LOG OUTPUT OF DEVICE COORDINATES ............................................................................ 80 Log output mode..................................................................................................... 80 8.4.2 9 Log output destination address ............................................................................... 80 DRAWING PROCESSING ..................................................................................................... 81 9.1 9.1.1 9.1.2 9.1.3 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.8 COORDINATE SYSTEM.................................................................................................... 81 Drawing coordinates ............................................................................................... 81 Texture coordinates ................................................................................................ 82 Frame buffer .......................................................................................................... 83 FIGURE DRAWING.......................................................................................................... 84 Drawing primitives................................................................................................. 84 Polygon drawing function ....................................................................................... 84 Drawing parameters ............................................................................................... 85 Anti-aliasing function ............................................................................................. 86 BIT MAP PROCESSING ................................................................................................... 87 BLT ........................................................................................................................ 87 Pattern data format ................................................................................................ 87 TEXTURE MAPPING........................................................................................................ 88 Texture size ............................................................................................................ 88 Texture color ........................................................................................................... 88 Texture lapping ...................................................................................................... 89 Filtering ................................................................................................................. 90 Perspective correction ............................................................................................. 90 Texture blending..................................................................................................... 91 Bi-linear high-speed mode ...................................................................................... 91 RENDERING.................................................................................................................. 93 Tiling...................................................................................................................... 93 Alpha blending ....................................................................................................... 93 Logic operation ....................................................................................................... 94 Hidden plane management..................................................................................... 94 DRAWING ATTRIBUTES ................................................................................................... 95 Line drawing attributes .......................................................................................... 95 Triangle drawing attributes.................................................................................... 95 Texture attributes................................................................................................... 96 BLT attributes ........................................................................................................ 97 Character pattern drawing attributes ..................................................................... 97 BOLD LINE ................................................................................................................... 98 Starting and ending points ..................................................................................... 98 Broken line pattern ................................................................................................ 99 Edging .................................................................................................................. 100 Interpolation of bold line joint............................................................................... 101 SHADOWING............................................................................................................... 102 9.8.1 Shadowing ............................................................................................................ 102 10 DISPLAY LIST.................................................................................................................... 103 10.1 10.1.1 10.1.2 10.2 10.2.1 10.2.2 10.3 10.3.1 10.3.2 11 OVERVIEW ................................................................................................................. 103 Header format ...................................................................................................... 104 Parameter format ................................................................................................. 104 GEOMETRY COMMANDS ............................................................................................... 105 Geometry command list ........................................................................................ 105 Explanation of geometry commands...................................................................... 108 RENDERING COMMAND ................................................................................................ 119 Command list ....................................................................................................... 119 Details of rendering commands............................................................................. 124 REGISTER ......................................................................................................................... 134 REGISTER LIST ........................................................................................................... 134 Host interface register list .................................................................................... 134 Graphics memory interface register list ................................................................ 136 Display controller register list .............................................................................. 137 Video Capture register list .................................................................................... 142 Drawing engine register list.................................................................................. 143 Geometry engine register list ................................................................................ 149 EXPLANATION OF REGISTER.......................................................................................... 150 Host interface registers......................................................................................... 151 Graphics memory interface registers .................................................................... 158 Display control register ......................................................................................... 161 Video Capture Registers ....................................................................................... 209 Drawing control registers ..................................................................................... 216 Drawing mode registers ........................................................................................ 219 Triangle drawing registers .................................................................................... 238 Line dr awing registers .......................................................................................... 241 Pixel drawing registers......................................................................................... 242 Rectangle drawing registers .............................................................................. 242 Blt registers ...................................................................................................... 243 High-speed 2D line drawing registers ................................................................ 244 High-speed 2D triangle drawing registers.......................................................... 245 Geometry control register .................................................................................. 246 Geometry mode registers ................................................................................... 248 Display list FIFO registers ................................................................................ 255 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 11.1.6 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.2.9 11.2.10 11.2.11 11.2.12 11.2.13 11.2.14 11.2.15 11.2.16 12 TIMING DIAGRAM .............................................................................................................. 256 12.1 HOST INTERFACE ........................................................................................................ 256 12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 12.1.6 12.1.7 12.1.8 12.1.9 12.1.10 12.1.11 12.1.12 12.1.13 12.1.14 12.1.15 12.1.16 12.1.17 12.1.18 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.2.7 12.3 12.3.1 12.3.2 12.3.3 12.4 12.5 12.6 12.7 12.8 12.9 CPU read/write timing diagram in SH3 mode (Normally Not Ready Mode)........... 256 CPU read/write timing diagram in SH3 mode (Normally Ready Mode) ................. 257 CPU read/write timing diagram in SH4 mode (Normally Not Ready Mode)........... 258 CPU read/write timing diagram in SH4 mode (Normally Ready Mode) ................. 259 CPU read/write timing diagram in V832 mode (Normally Not Ready Mode) ......... 260 CPU read/write timing diagram in V832 mode (Normally Ready Mode) ................ 261 CPU read/write timing diagram in SPARClite (Normally Not Ready Mode) .......... 262 CPU read/write timing diagram in SPARClite (Normally Ready Mode) ................. 263 SH4 single-address DMA write (transfer of 1 long word)....................................... 264 SH4 single-address DMA write (transfer of 8 long words) .................................. 265 SH3/4 dual-address DMA (transfer of 1 long word) ............................................ 266 SH3/4 dual-address DMA (transfer of 8 long words)........................................... 266 V832 DMA transfer ........................................................................................... 267 SH4 single-address DMA transfer end timing .................................................... 268 SH3/4 dual-address DMA transfer end timing ................................................... 268 V832 DMA transfer end timing.......................................................................... 269 SH4 dual DMA write without ACK .................................................................... 270 Dual-address DMA (without ACK) end timing ................................................... 271 Timing of read access to same row address ........................................................... 272 Timing of read access to different row addresses ................................................... 273 Timing of write access to same row address .......................................................... 274 Timing of write access to different row addresses.................................................. 275 Timing of read/write access to same row address .................................................. 276 Delay between ACTV commands........................................................................... 277 Delay between Refresh command and next ACTV command................................. 277 DISPLAY TIMING .......................................................................................................... 278 Non-interlace mode............................................................................................... 278 Interlace video mode ............................................................................................. 279 Composite synchronous signal .............................................................................. 280 CPU CAUTIONS .......................................................................................................... 280 SH3 MODE ................................................................................................................ 281 SH4 MODE ................................................................................................................ 281 V832 MODE............................................................................................................... 282 SPARCLITE ............................................................................................................... 282 SUPPORTED DMA TRANSFER MODES ............................................................................ 282 GRAPHICS MEMORY INTERFACE..................................................................................... 272 13 ELECTRICAL CHARACTERISTICS .................................................................................... 283 13.1 13.2 INTRODUCTION ........................................................................................................... 283 MAXIMUM RATING........................................................................................................ 283 13.3 13.3.1 13.3.2 13.4 13.4.1 13.4.2 13.5 13.5.1 13.5.2 13.5.3 13.5.4 13.5.5 13.6 13.7 13.7.1 13.7.2 13.7.3 13.7.4 RECOMMENDED OPERATING CONDITIONS ....................................................................... 284 Recommended operating conditions ...................................................................... 284 Note at power-on .................................................................................................. 284 DC CHARACTERISTICS ................................................................................................. 285 DC Characteristics ............................................................................................... 285 V-I characteristics diagram ................................................................................... 286 AC CHARACTERISTICS ................................................................................................. 287 Host interface ....................................................................................................... 287 Video interface...................................................................................................... 288 Video Capture Interface........................................................................................ 289 Graphics memory interface................................................................................... 290 PLL specifications................................................................................................. 294 AC CHARACTERISTICS MEASURING CONDITIONS ............................................................. 295 TIMING DIAGRAM......................................................................................................... 296 Host interface ....................................................................................................... 296 Video interface...................................................................................................... 300 Video Capture Interface........................................................................................ 301 Graphics memory interface................................................................................... 302 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1 GENERAL 1.1 Preface Coral graphics controller has some functions and optional efficiency and is planned to be serial-manufactured according to purposes. The MB86294S is graphics controller LSI which is added the I C interface function to the MB86294. For detail of the I C interface function, please refer an another additional manual for MB86294S. 2 2 Note) Purchase of Fujitsu I C components conveys a license under the Philips I C Patent Right to use these 2 2 components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. 2 2 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 11 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.2 Features * Geometry engine Geometry engine supports the geometry processing that is compatible with ORCHID (MB86292). Using the display list created by ORCHID enables drawing. **(But Floating point setup command is deleted.) Heavy processing of geometric operations such as coordinates conversions or clipping performed by this device can reduce the CPU loads dramatically. * 2D and 3D Drawing Coral has a drawing function that is compatible with the CREMSON ( B86290A). It can draw data M using the display list created for CREMSON. **(But Internal texture RAM is deleted.) Coral also supports 3D rendering, such as texture mapping with perspective collection and Gouraud shading, alpha blending, and anti-aliasing for drawing smooth lines. * Display controller Coral has a display controller that is compatible with ORCHID. In addition to the traditional XGA (1024 x 768 pixels) display, 4-layer overlay, left/right split display, wrap-around scrolling, double buffers, and translucent display, function of 6 -layer overlay, 4-siding for palette are expanded. * Digital video capture Digital video capture function can store digital video data such as TV in graphics memory; it can display rendered graphics and video graphics on the same screen. * Host CPU interface Can be connected to SH3 and SH4 manufactured by Hitachi, to V832 microprocessor by NEC and to SPARClite (MB86833) by Fujitsu without external circuits. * External memory interface SDRAM and FCRAM can be connected. * Others CMOS technology with 0.18-m Package: BGA 256 pin, HQFP 256 pin Supply voltage: 1.8 V (internal operation) /3.3 V (I/O) Current consumption ( TYPICAL ) 1.8 V power supply : 500mA 3.3V power supply : 100mA MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 12 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.3 Block Diagram CORAL general block diagram is shown below: Pixel Bus External Bus of Host CPU A2-25 Host Interface D0-31 DRGB Capture Controller YUV Display Controller DAC MD0-31/63 ARGB SDRAM or FCRAM External Memory MA0-14 Geometry Engine 2D/3D Rendering Engine Controller Fig.1.1 CORAL Block Diagram MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 13 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.4 Functional O verview 1.4.1 Host CPU interface Supported CPU Coral can be connected to SH3 and SH4 manufactured by HITACHI, V832 by NEC, SPARClite (MB86833) by Fujitsu. External Bus Clock Can be connected at max. 100 MHz (when using SH4 interface) Ready Mode Supports normal ready/not ready. Endian Supports little endian. Access Mode SRAM interface FIFO interface (transfer destination address fixed) DMA transfer Supports 1-double word (32 bits) /8-double word (32 bytes) (only SH4) for transfer unit. ACK used/unused mode can be selected as protocol (only for DAM in dual address mode) Supports dual address/mode single address mode (only SH4). Supports cycle steel/burst. Supports local display list transfer. Interrupt Vertical (frame) synchronous detection Field synchronous detection External synchronous error detection Drawing command error Drawing command execution end MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 14 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Switching internal operating frequency Switch the operating frequency immediately after a reset (before rewriting MMR mode register of external memory interface). Any operating frequency can be selected from the five combinations shown in Table 2-6. Table 1-1 Frequency Setting Combinations Clock for other than geometry engine 133 MHz 100 MHz 133 MHz 100 MHz 100 MHz Clock for geometry engine 166 MHz 166 MHz 133 MHz 133 MHz 100 MHz The following relationship is disabled: Clock for geometry engine < Clock for other than geometry engine MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 15 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.4.2 External memory interface SDRAM or FCRAM can be connected. 64 bits or 32 bits can be selected for data bus. Max. 133 MHz is available for operating frequency. Connectable memory configuration is as shown below. External Memory Configuration Type FCRAM 16 Mbits (x16 Bits) FCRAM 16 Mbits (x16 Bits) SDRAM 64 Mbits (x32 Bits) SDRAM 64 Mbits (x32 Bits) SDRAM 64 Mbits (x16 Bits) SDRAM 64 Mbits (x16 Bits) SDRAM 128 Mbits (x32 Bits) SDRAM 128 Mbits (x32 Bits) SDRAM 128 Mbits (x16 Bits) SDRAM 128 Mbits (x16 Bits) SDRAM 256 Mbits (x16 Bits) Data bus width 32 Bits 64 Bits 32 Bits 64 Bits 32 Bits 64 Bits 32 Bits 64 Bits 32 Bits 64 Bits 32 Bits Use count 2 4 1 2 2 4 1 2 2 4 2 Total capacity 4 Mbytes 8 Mbytes 8 Mbytes 16 Mbytes 16 Mbytes 32 Mbytes 16 Mbytes 32 Mbytes 32 Mbytes 64 Mbytes 64 Mbytes MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 16 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.4.3 Display controller Video data output Analog RGB video output is provided. And setting graphics memory bus to 32 bits, digital RGB video output is also provided. Screen resolution LCD panels with wide range of resolutions are supported by using a programmable timing generator as follows: Screen Resolutions Resolutions 1024 x 768 1024 x 600 800 x 600 854 x 480 640 x 480 480 x 234 400 x 234 320 x 234 Hardware cursor Coral supports two hardware cursor functions. Each of these hardware cursors is specified as a 64 x 64-pixel area. Each pixel of these hardware cursors is 8 bits and uses the same look-up table as indirect color mode. Double buffer method Double buffer method in which drawing window and display window is switched in units of 1 frame enables the smooth animation. Flipping (switching of display window area) is performed in synchronization with the vertical blanking period using program. Scroll method Independent setting of drawing and display windows and their starting position enables the smooth scrolling. Display colors * Supports indirect color mode which uses the look-up table (color palette) in 8 bits/pixels. * Entry for look-up table (color palette) corresponds to color code for 8 bits, in other words, 256. data is each 6 bits of RGB. Consequently, 256 colors can be displayed out of 260,000 colors. * Supports direct color mode which specifies RGB with 16 bits/pixels. Color MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 17 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Overlay Compatibility mode Up to four extra layers (C, W, M and B) can be displayed overlaid. The overlay position for the hardware cursors is above/below the top layer (C). The transparent mode or the blend mode can be selected for overlay. The M- and B-layers can be split into separate windows. Window display can be performed for the W-layer. Two palettes are provided: C -layer and M-/B-layer. The W-layer is used as the video input layer. L0, L2, L4 (0,0) L1 (WX, WY) L3, L5 (HDB +1, 0) Window mode * Up to six screens (L0 to 5) can be displayed overlaid. * The overlay sequence of the L0- to L5-layers can be changed arbitrarily. * The overlay position for the hardware cursors is above/below the L0-layer. * The transparent mode or the blend mode can be selected for overlay. * The L5-layer can be used as the blend coefficient plane (8 bits/pixel). * Window display can be performed for all layers. * Four palettes corresponded to L0 to 3 are provided. * The L1-layer is used as the video input layer. * Background color display is supported in window display for all layers. L0 (L0WX, L0WY) L5 (L5WX, L5WY) L4 (L4WX, L4WY) L2 (L2WX, L2WY ) L1 (L1WX, L1WY ) L3 (L3WX, L3WY ) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 18 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.4.4 Video Capture The video capture function captures ITU RBT-656 format videos. Video data is stored in graphics memory once and then displayed on the screen in synchronization with the display scan. Both NTSC and PAL video formats are supported. 1.4.5 Geometry processing Coral has a geometry engine for performing the numerical operations required for graphics processing. The geometry engine uses the floating-point format for highly precise operations. It selects the required geometry processing according to the set drawing mode and primitive type and executes processing to the final drawing. Primitives Point, line, line strip, independent triangle, triangle strip, triangle fan, and arbitrary polygon are supported. MVP Transformation MVP Transformation Setting a 4 x 4 transformation matrix enables transformation of a 3D model view projection. Two-dimensional affine transformation is also possible. Clipping Clipping stops drawing of figures outside the window (field of view). Polygons (including concave shapes) can also be clipped. Culling Triangles on the back are not drawn. 3D-2D Transformation This functions transforms 3D coordinates (normalization) into 2D coordinates in orthogonal or perspective projections. View port transformation This function transforms normalized 2D coordinates into drawing (device) coordinates. Primitive setup This function automatically performs a variety of slope computations, etc., based on transforming vertex data into coordinates and prepares for rendering (setup). Log output of device coordinates The view port conversion results are output to the local memory. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 19 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.4.6 2D Drawing 2D Primitives Coral can perform 2D drawing for graphics memory (drawing plane) in direct color mode or indirect color mode. Bold lines with width and broken lines can be drawn. With anti-aliasing smooth diagonal lines also can be drawn. A triangle can be tiled in a single color or 2D pattern (tiling), or mapped with a texture p attern by specifying coordinates of the 2D pattern at each vertex (texture mapping). At texture mapping, drawing/non-drawing can be set in pixel units. Moreover, transparent processing can be performed using alpha blending. When drawing in single color or tiling without Gouraud shading or texture mapping, high-speed 2DLine and high-speed 2DTriangle can be used. Only vertex coordinates are set for these primitives. High-speed 2DTriangle is also used to draw polygons. 2D Primitives Primitive type Point Line Bold line strip (provisional name) Triangle High-speed 2DLine Arbitrary polygon Description Plots point Draws line Draws continuous bold line This primitive is used when interpolating the bold line joint. Draws triangle Draws lines Compared to line, this reduces the host CPU processing load. Draws arbitrary closed polygon containing concave shapes consisting of vertices Arbitrary polygon drawing Using this function, arbitrary closed polygon containing concave shapes consisting of vertices can be drawn. (There is no restriction on the count of vertices, however, the polygon with its sides crossed are not supported.) In this case, as a work area for drawing, polygon drawing flag buffer is used on the graphics memory. In drawing polygon, draw triangle for polygon drawing flag buffer using high-speed 2DTriangle. Decide any vertex as a starting point to draw triangle along the periphery. It enables you to draw final polygon form in single color or with tiling/texture mapping in a drawing frame. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 20 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL BLT/Rectangle drawing This function draws a rectangle using logic operations. It is used to draw pattern and copy the image pattern within the drawing frame. It is also used for clearing drawing frame and Z buffer. BLT Attributes Attribute Raster operation Transparent processing Alpha blending Description Selects two source logical operation mode Performs BLT without drawing pixel consistent with the transparent color. The alpha map and source in the memory is subjected to alpha blending and then copied to the destination. Pattern (Text) drawing This function draws a binary pattern (text) in a specified color. Pattern (Text) Drawing Attributes Attribute Enlarge Description Vertically 2 x 2 Horizontally x 2 Vertically and Horizontally x 2 Vertically 1/2 x 1/2 Horizontally 1/2 Vertically and Horizontally 1/2 Shrink Drawing clipping This function sets a rectangle frame in drawing frame to prohibit the drawing of the outside the frame. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 21 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.4.7 3D Drawing 3D Primitives This function draws 3D objects in drawing memory in the direct color mode. 3D Primitives Primitive Point Line Triangle Arbitrary polygon Description Plots 3D point Draws 3D line Draws 3D triangle Draws arbitrary closed polygon containing concave shapes consisting of vertexes 3D Drawing attributes Texture mapping with bi-linear filtering/automatic perspective correction and Gouraud shading provides high-quality realistic 3D drawing. A built-in texture mapping unit performs fast pixel calculations. This unit also delivers color blending between the shading color and texture color. Hidden plane management Coral supports the Z buffer for hidden plane management. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 22 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.4.8 Special effects Anti-aliasing Anti-aliasing manipulates line borders of polygons in sub-pixel units and blend the pre-drawing pixel color with color to make the jaggies be seen smooth. It is used as a functional option for 2D drawing (in direct color mode only). Bold line and broken line drawing This function draws lines of a specific width and a broken line. Line Drawing Attributes Attribute Line width Broken line Description Selectable from 1 to 32 pixels Set by 32 bit or 24 bit of broken line pattern * Supports the verticality of starting and ending points. * Supports the verticality of broken line pattern. * Interpolation of bold line joint supports the following modes: (1) Broken line pattern reference address fix mode The same broken line pattern is kept referencing for the period of some pixels starting from the joint and the starting point for the next line. (2) No interpolation * Supports the equalization of the width of bold lines. * Supports the bold line edging. * Not support the Anti-aliasing of dashed line patterns. * For a part overlaid due to connection of bold lines, natural overlay can be represented by providing depth information. (Z value). Shading Supports the shading primitive. Drawing is performed to the body primitive coordinates (X, Y) with an offset as a shade. At this drawing, the Z buffer is used in order to differentiate between the body and shade. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 23 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Alpha blending Alpha blending blends two image colors to provide a transparent effect. CORAL supports two types of blending; blending two different colors at drawing, and blending overlay planes at display. Transparent color is not used for these blending options. There are two ways of specifying alpha blending for drawing: (1) Set a transparent coefficient to the register; the transparent coefficient is applied for transparency processing of one plane. (2) Set a transparent coefficient for each vertex of the plane; as with Gouraud shading, the transparent coefficient is linear-interpolated to perform transparent processing in pixel units. In addition to the above, the following settings can be performed at texture mapping. When the most significant bit of each texture cell is 1, drawing or transparency can be set. When the most significant bit of each texture cell is 0, non-drawing can be set. Alpha Blending Type Drawing Description Transparent ratio set in particular register While one primitive (polygon, pattern, etc.), being drawn, registered transparent ratio applied A transparent coefficient set for each vertex. A linear-interpolated transparent coefficient applied. This is possible only in direct color mode. Overlay display Blends top layer pixel color with lower layer pixel color Transparent coefficient set in particular register Registered transparent coefficient applied during one frame scan Gouraud Shading Gouraud shading can be used in the direct color mode to provide 3D object real shading and color gradation. Gray Scale Gouraud Shading Gray scale gouraud shading can be used in the in-direct color(8bit/pixel) mode to draw a blend coefficient layer. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 24 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Texture mapping Coral supports texture mapping to map a image pattern onto the surface of plane. The texture n pattern can be laid out in the graphics memory. In this case, max. 4096 x 4096 pixels can be used. For drawing 8-bit color, only point sampling can be specified for texture interpolation; only de-curl can be specified for the blend mode. Texture Mapping Function Filtering Coordinates correction Blend Description Point sample Bi-linear filter Linear Perspective De-curl Modulate Stencil Normal Stencil Stencil alpha Repeat Cramp Border Alpha blend Wrap MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 25 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1.4.9 Others Drawing color 8-bit indirect color and 16-bit direct color are supported as a drawing input data. Top-left rule non-applicable mode In addition to the top-left rule applicable mode in which the triangle borders are compatible with CREMSON, the top-left rule non-applicable mode can be used. (In case of non-top-left polygon drawing, an object has to be in a geometry clipping area.) Caution: Use perspective correct mode when use texture at the top-left rule non-applicable mode. Top-left rule non-applicable primitives cannot use Geometry clip function. Non-top-left-part's pixel quality is less than body. (using approximate calculation) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 26 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2 PINS 2.1 S i g n a l s 2.1.1 Signal lines DCLKO D0-31 A2-25 BCLKI XRST XCS XRD Host CPU interface XWE0 -3 XRDY XBS DREQ DRACK DTACK XINT RDY_MODE BS_MODE CLK Clock S CKM CLKSEL0-1 (MD63-32)* MD31-0 MA0-14 MRAS MCAS MWE MDQM7*,6*,5-0 MCLKO MCLKI Test TESTH CCLK (VI7-0)* PBGA/HQFP256 DCKLI HSYNC VSYNC CSYNC DISPE GV (R7-0)* G(7-0)* * means these pins are multiplexed. Video output interface CORAL-LB Graphics Controller B(7-0)* XRGBEN AOUTR/G/B COMPR/G/B VR Graphics memory interface Video Capture interface Fig. 2.1 CORAL Signal Lines MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 27 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.2 P i n A s s i g n m e n t 2.2.1 PBGA256 Pin assignment diagram (TOP_VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 77 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 57 78 145 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 127 56 79 146 205 256 255 254 253 252 251 250 249 248 247 246 245 244 189 126 55 80 147 206 81 148 207 82 149 208 83 150 209 84 151 210 85 152 211 86 153 212 87 154 213 88 155 214 89 156 215 90 157 216 91 158 217 243 188 125 54 242 187 124 53 241 186 123 52 240 185 122 51 Thermal Balls In order to reduce heat, please connect these pins to GND 239 184 121 50 238 183 120 49 237 182 119 48 236 181 118 47 235 180 117 46 234 179 116 45 233 178 115 44 232 177 114 43 92 159 218 219 220 221 222 223 224 225 226 227 228 229 230 231 176 113 42 93 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 112 41 94 21 95 22 96 23 97 24 98 25 99 100 101 102 103 104 105 106 107 108 109 110 111 40 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Note: The MODE2 signal used for Orchid is changed as shown below. MODE2 signal for Orchid RDY_MODE signal for Coral MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 28 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.2.2 PBGA256 Pin assignment table Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 A B C D E F G H J K L M N P R T U V W Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y W V U T R P N M L K J H G F E D C B A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 19 18 17 16 15 14 Pin Name OPEN VSYNC GV XINT VDDH XRD D1 D3 D6 VDDL VSS D8 D11 D13 D16 D20 D22 D25 D28 VSS DTACK A3 A7 A9 A12 A15 A17 A20 A22 VDDL A23 XRST CLK VSS MD0 MD3 MD6 MD9 VSS MD17 MD20 MD24 MD26 MD30 MCLKI VDDH DQM1 DQM3 VDDL MA0 MA4 MA6 VDDH MA12 MRAS DQM4 DQM7 / B1 VSS MD38 / G0 MD41 / G3 MD44 / G6 MD46 / R0 MD50 / R4 MD53 / R7 Pin No 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 A A A A A A A A A A A A B C D E F G H J K L M N P R T U V W W W W W W W W W W W W W W W W W W V U T R P N M L K J H G F E D C B 13 12 11 10 9 8 7 6 5 4 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 Pin Name MD54 MD57 / VI1 VDDL MD59 / VI3 MD60 / VI4 VDDL TESTH TESTH AVS2 COMPG VRO COMPR MODE1 MODE2 DE DCLKO DREQ XCS XBS D2 D5 D9 D12 D15 D17 D21 VDDL D26 D30 XWE0 XWE1 A2 A5 A8 A11 A13 A16 A19 A24 PLLVSS VDDL CLKSEL0 MD1 MD4 MD7 MD11 MD14 MD15 MD19 MD22 MD25 MD29 MD31 VSS DQM0 MA1 MA5 MA8 MA9 MA13 MCAS DQM5 VDDH MD34 / B4 Pin No 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 B B B B B B B B B B B B B B B B C D E F G H J K L M N P R T U V V V V V V V V V V V V V V V V U T R P N M L K J H G F E D C C C 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 17 16 Pin Name MD35 / B5 MD40 / G2 MD42 / G4 MD45 / G7 MD49 / R3 VDDL VDDH MD56 / VI0 MD61 / VI5 CCLK TESTH AOUTB AOUTG AOUTR AVS0 BS_MODE MODE0 DCLKI HSYNC CSYNC XRDY BCLKI D0 D4 VDDH D14 D18 VDDH D24 D27 D31 VSS XWE2 DRACK A4 A6 VDDH VDDL A18 A25 S CLKSEL1 MD2 MD5 MD8 MD12 MD13 VDDH MD18 MD21 VDDL MD28 VDDL MCLKO MA2 MA7 MA10 MA14 MWE DQM6 / B0 MD32 / B2 MD33 / B3 MD36 / B6 MD39 / G1 Pin No 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 C C C C C C C C C C C C D E F G H J K L M N P R T U U U U U U U U U U U U U U T R P N M L K J H G F E D D D D D D D D D D D D D 15 14 13 12 11 10 9 8 7 6 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17 16 15 14 13 12 11 10 9 8 7 6 5 Pin Name VDDL VDDH MD48 / R2 MD52 / R6 MD55 MD62 / VI6 TESTH AVD2 AVD1 AVD0 VREF RDY_MODE VSS VDDH VSS VDDL VSS VDDL D7 D10 VDDL VSS D23 D19 D29 VSS XWE3 A10 VDDL VSS A14 A21 CKM PLLVDD VSS VDDL VDDH MD10 VSS MD16 MD27 MD23 VSS VSS DQM2 MA3 VDDL VSS VDDL MA11 VSS VSS MD37 / B7 MD47 / R1 MD43 / G5 VSS MD51 / R5 MD58 / VI2 MD63 / VI7 TESTH VSS AVS1 COMPB XRGBEN MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 29 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.2.3 HQFP256 Pin assignment diagram RDY_MODE BS_MODE MD46 / R0 MD45 / G7 MD44 / G6 VDDH MD43 / G5 VSS MD42 / G4 VDDL MD41 / G3 MD40 / G2 MD39 / G1 MD38 / G0 MD53 / R7 MD52 / R6 MD51 / R5 VDDL MD50 / R4 MD49 / R3 MD48 / R2 MD47 / R1 VDDL MD63 / VI7 MD62 / VI6 MD61 / VI5 MD60 / VI4 MD59 / VI3 VDDL MD58 / VI2 MD57 / VI1 MD56 / VI0 MD37 / B7 MD36 / B6 196 195 MD35 / B5 MD34 / B4 194 193 XRGBEN COMPR AVS1 COMPG AVD1 AOUTG AOUTR OPEN MODE0 AVS2 COMPB AVD2 AOUTB TESTH TESTH TESTH TESTH TESTH VDDH VSS 218 217 VSS CCLK MD55 MD54 220 219 VREF AVS0 251 250 VRO AVD0 249 248 256 255 254 253 252 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 MODE1 MODE2 DCLKI VDDH VSYNC HSYNC DE GV CSYNC DCLKO VSS VDDL XRDY XINT DREQ VDDH VSS BCLKI XCS XRD XBS VDDL D0 D1 VSS D2 D3 D4 D5 D6 D7 VDDL VSS D8 D9 VDDH D10 D11 D12 VSS D13 D14 VDDL D15 D16 D17 D18 D19 D20 D21 VDDH D22 D23 VSS VDDL D24 D25 D26 D27 D28 D29 D30 D31 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 99 100 101 102 103 104 105 106 107 108 VSS 109 CLKSEL0 110 CLKSEL1 111 VDDH 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 198 197 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 MD33 / B3 MD32 / B2 VDDH VSS DQM7 / B1 DQM6 / B0 DQM5 DQM4 MWE MCAS VSS VDDL MRAS MA14 MA13 MA12 MA11 MA10 MA9 VDDH MA8 VDDL MA7 MA6 VSS MA5 MA4 MA3 MA2 MA1 MA0 VDDL DQM3 DQM2 DQM1 DQM0 MCLKO VDDH VSS VSS MCLKI VDDL VSS MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 VDDL MD23 VSS MD22 MD21 MD20 MD19 MD18 MD17 MD16 VDDH MD15 MD14 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 PLLVDD VDDL DRACK A2 XWE3 DTACK PLLVSS VSS VDDH A11 VDDL A6 VDDL A15 VDDL A23 VDDL VSS MD10 MD11 Note: The MODE2 signal used for Orchid is changed as shown below. MODE2 signal for Orchid RDY_MODE signal for Coral MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 30 MD12 MD13 XWE0 XWE1 XWE2 CKM XRST MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 CLK S A5 VSS VSS A16 A9 A10 A12 A13 A14 A17 A18 A19 A20 A21 A22 A24 A25 A3 A4 A7 A8 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.2.4 HQFP256 Pin assignment table Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name MODE1 MODE2 DCLKI VDDH VSYNC HSYNC DE GV CSYNC DCLKO VSS VDDL XRDY XINT DREQ VDDH VSS BCLKI XCS XRD XBS VDDL D0 D1 VSS D2 D3 D4 D5 D6 D7 VDDL VSS D8 D9 VDDH D10 D11 D12 VSS D13 D14 VDDL D15 D16 D17 D18 D19 D20 D21 VDDH D22 D23 VSS VDDL D24 D25 D26 D27 D28 D29 D30 D31 VSS Pin No 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name XWE0 XWE1 XWE2 XWE3 DTACK DRACK A2 A3 A4 A5 VSS VDDL A6 A7 A8 A9 A10 VDDH A11 A12 A13 A14 VDDL A15 VSS A16 A17 A18 A19 A20 A21 A22 VDDL A23 A24 A25 CKM XRST PLLVSS VSS CLK S PLLVDD VDDL VSS CLKSEL0 CLKSEL1 VDDH MD0 MD1 MD2 MD3 VDDL VSS MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 Pin No 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 Pin Name MD14 MD15 VDDH MD16 MD17 MD18 MD19 MD20 MD21 MD22 VSS MD23 VDDL MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 VSS VDDL MCLKI VSS VSS VDDH MCLKO DQM0 DQM1 DQM2 DQM3 VDDL MA0 MA1 MA2 MA3 MA4 MA5 VSS MA6 MA7 VDDL MA8 VDDH MA9 MA10 MA11 MA12 MA13 MA14 MRAS VDDL VSS MCAS MWE DQM4 DQM5 DQM6 / B0 DQM7 / B1 VSS VDDH MD32 / B2 MD33 / B3 Pin No 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Pin Name MD34 / B4 MD35 / B5 MD36 / B6 MD37 / B7 MD38 / G0 MD39 / G1 MD40 / G2 MD41 / G3 VDDL MD42 / G4 VSS MD43 / G5 VDDH MD44 / G6 MD45 / G7 MD46 / R0 MD47 / R1 MD48 / R2 MD49 / R3 MD50 / R4 VDDL MD51 / R5 MD52 / R6 MD53 / R7 VSS VDDH MD54 MD55 MD56 / VI0 MD57 / VI1 MD58 / VI2 VDDL MD59 / VI3 MD60 / VI4 MD61 / VI5 MD62 / VI6 MD63 / VI7 VDDL CCLK VSS TESTH TESTH TESTH TESTH TESTH AOUTB AVD2 COMPB AVS2 AOUTG AVD1 COMPG AVS1 OPEN AOUTR AVD0 VRO AVS0 VREF COMPR XRGBEN BS_MODE RDY_MODE MODE0 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 31 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Notes VSS/PLLV SS VDDH VDDL/PLLV DD PLLV DD OPEN TESTH AVS AVD : : : : Ground 3.3-V power supply 1.8-V power supply : PLL power supply (1.8 V) : Do not connect anything. : Input a 3.3 V-power supply. : Analog Ground Analog power supply (3.3 V) - It is recommended that PLLV DD should be isolated on the PCB. It is recommended that AVD should be isolated on the PCB. - Insert a bypass capacitor with good high frequency characteristics between the power supply and ground. Place the capacitor as near as possible to the pin. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 32 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.3 P i n F u n c t i o n 2.3.1 Host CPU interface Table 2-1 Host CPU Interface Pins Pin name MODE0-2 RDY_MODE BS_MODE XRST D0-31 A2-A25 BCLKI XBS XCS XRD XWE0 XWE1 XWE2 XWE3 XRDY Input Input Input Input In/Out Input Input Input Input Input Input Input Input Input Output Tri-state I/O Host CPU mode select Normally ready, Not ready select BS signal with/without select Hardware reset Host CPU bus data Host CPU bus address (In th e V832 mode, A[24] is connected to XMWR.) Host CPU bus clock Bus cycle start signal Chip select signal Read strobe signal Write strobe for D0 to D7 signal Write strobe for D8 to D15 signal Write strobe for D16 to D23 signal Write strobe for D24 to D31 signal Wait request signal (In the SH3 mode, when this signal is "0", it indicates the wait state; in the SH4, V832 and SPARClite modes, when this signal is "1", it indicates the wait state.) DMA request signal (This signal is low-active in both the SH mode and V832 mode.) Acknowledge signal in response to DMA request (DMAAK is used in the V832 mode; this signal is high-active in both the SH mode and V832 mode.) DMA transfer strobe signal (XTC is used in the V832 mode. In the SH mode, this signal is high-active; in the V832 mode, it is low-active.) Interrupt signal issued to host CPU (In the SH mode, and SPARClite this signal is low-active; in the V832 mode, it is high-active) Description DREQ DRACK/DMAAK Output Input DTACK/XTC Input XINT Output MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 33 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL * Coral can be connected to the Hitachi SH4 (SH7750), SH3 (SH7709) NEC V832 and Fujitsu SPARClite (MB86833) without external circuit. In the SRAM interface mode, Coral can be used with any other CPU as well. The host CPU is specified by the MODE0 to 2 pins. MODE 2 L L L L H L L H H X MODE 1 L H L H X MODE 0 SH3 SH4 V832 SPARClite Reserved CPU When the bus cycle terminates, a ready signal level can be set. When using the RDY_MODE signal at "High" level, set two cycles as the CPU software wait of the CPU. (When BS_MODE = "High" level, set the CPU software wait to three cycles.) RDY_ MODE L H Ready signal mode When the bus cycle terminates, sets the XRDY signal to the `not ready' level. When the bus cycle terminates, sets the XRDY signal to the `ready' level. A CPU with no BS (Bus Start) pin can be used. Setting can be performed in all CPU modes. Connection can be made to a CPU with no BS signal by setting the BS_MODE signal to "High" level. When not using the BS signal, fix the BS pin of CORAL at "High" level. When using the BS_MODE signal as "High" level in the normally ready mode, set the CPU software wait to three cycles. BS_ MODE L H BS signal mode Connect to a CPU with the BS signal Connect to a CPU without the BS signal The data signal is 32 bits (fixed). The address signal is 32 bits (per one double-word) x 24, and has a 64-Mbyte address field. address space is provided for V832 and SPARClite.) The external bus operating frequency is up to 100 MHz. In the SH4, V832, and SPARClite modes, when the XRDY signal is low, it is in the ready state. However, in the SH3 mode, when the XRDY signal is low, it is in the wait state. This signal is a tri-state output that is synchronized with the rising edge of BCLKI. DMA data transfer is supported using an external DMA controller. An interrupt signal is generated to the host CPU. The XRST input must be kept low for at least 300 s after setting the S (PLL reset) signal to high. In the V832 mode, Coral signals are connected to the V832 CPU as follows: CORAL Pins A24 DTACK DRACK XMWR XTC DMAAK V832 Signals (16-MByte MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 34 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.3.2 Video output interface Table 2-2 Video Output Interface Pins Pin name DCLKO DCLKI HSYNC VSYNC CSYNC DISPE GV R7-0 G7-0 B7-0 I/O Output Input I/O I/O Output Output Output Output Output Output Description Dot clock signal for display Dot clock signal input Horizontal sync signal output Horizontal sync input XRGBEN AOUTR AOUTG AOUTB ACOMPR ACOMPG ACOMPB VREF VRO Input Analog Output Analog Output Analog Output Analog Analog Analog Analog Analog It is possible to output digital RGB, when XRGBEN = 0.(Memory bus=32bit) Additional setting of external circuits can generate composite video signal. Synchronous to external video signal display can be performed. Either mode which is synchronous to DCLKI signal or one which is synchronous to dot clock, as for normal display can be selected. Since HSYNC and VSYNC signals are set to input state after reset, these signals must be pulled up LSI externally. The GV signal switches graphics and video at chroma key operation. When video is selected, the "Low" level is output. AOUTR, AOUTG and AOUTB must be terminated at 75 ohm. 1.1-V is input to VREF. A bypass capacitor( with good high-frequency characteristics) must be inserted between VREF and AVS. ACOMPR, ACOMPG and ACOMPB are tied to analog VDD via 0.1uF ceremic capacitors. VRO must be pulled down to analog ground by a 2.7 k ohm resister. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 35 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.3.3 Video Capture interface Table 2-3 Video Capture Interface Pins Pin name CCLK VI7-0 I/O Input Input Description Digital video input clock signal input ITU656 Digital video data input. These pins are multiplexed MD63-MD56. Inputs ITU-RBT-656 format digital video signal Digital video data input can be used only when the XRGBEN pin is "0". the digital video data input pins. MD63-MD56 are assigned as When video capture is not used and the XRGBEN pin is 0, input the "High" level to MD63-MD56. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 36 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.3.4 Graphics memory interface Table 2-3 Graphics memory interface pins Pin name MD31-0 MD53-32 MD55-54 MD63-56 MA0-14 MRAS MCAS MWE MDQM5-0 MDQM7-6 MCLK0 MCLK1 I/O I/O I/O I/O Output Output Output Output Output Output Output Input I/O Description Graphics memory bus data Graphics memory bus data or digital R7-0, G7-0, B7-2 output (when XRGBEN pin = 0) Graphics memory bus data Graphics memory bus data or video capture input (when XRGBEN pin =0) Graphics memory bus data Row address strobe Column address strobe Write enable Data mask Data mask or digital B1-0 output(when XRGBEN=0) Graphics memory clock output Graphics memory clock input Connect the interface to the external memory used as memory for image data. The interface can be connected to 64-/128-/256-Mbit SD RAM ( 6- or 32-bit length data bus) without using any external 1 circuit. 64 bits or 32 bits can be selected for the memory bus data. Connect MCLKI to MCLK0. - When memory bus width is 32 bit and digital RGB output is used ( XRGBEN="0"), MD54-63 pins are set to "high level", and MD32-53 pins and MDQM4-7 pins are set to open. - When memory bus width is 32 bit and digital RGB output is not used ( XRGBEN="1"), MD32-63 pins and MDQM4-7 pins are set to open. When XRGBEN is fixed at "1", MD63-MD32 and MDQM7-MDQM6 can be used as graphics memory interface. When XRGBEN is fixed at "0", these signals can be used as digital RGB output and video capture data input. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 37 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.3.5 Clock input Table 2-4 Pin name CLK S CKM CLKSEL [1:0] I/O Input Input Input Input Clock input signal PLL reset signal Clock mode signal Clock rate select signal Clock Input Pins Description Inputs source clock for internal operation clock and display dot clock. Normally, 4 Fsc (= 14.31818 MHz: NTSC) is input. An internal PLL generates the internal operation clock of 166 MHz/133 MHz and the display base clock of 400 MHz. CKM L H Clock mode Output from internal PLL selected Host CPU bus clock (BCLK1) selected * When CKM = L, selects input clock frequency when built-in PLL used according to setting of CLKSEL pins CLKSEL1 L L H H CLKSEL0 L H L H Input clock frequency Inputs 13.5-MHz clock frequency Inputs 14.32-MHz clock frequency Inputs 17.73-MHz clock frequency Reserved Multiplication rate x 29 x 28 x 22 Display reference clock 391.5 MHz 400.96 MHz 390.06 MHz MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 38 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 2.3.6 Test pins Table 2-5 Test Pins Pin name TESTH I/O Input Input 3.3-V power. Description 2.3.7 Reset sequence See "13.3.2 Note at power-on". MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 39 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 3 PROCEDURE OF THE HA RDWARE INITIALIZATION 3.1 Hardware reset 1.Do the hardware reset. (see section 13.3.2) 2.After the hardware reset, set the CCF(Change of Frequency) register (section 11.2.1). In being unstable cycle after the hardware reset, keep 32 bus cycles open. 3.Set the graphics memory interface register, MMR (Memory I/F Mode Register). After setting the CCF register, take 200 us to set the MMR register. In being unstable memory access cycle, keep 32 bus cycles open. 4.Other registers, except for the CCF register and the MMR register, should be set after setting the CCF register. In case of not using memory access, the MMR register could be set in any order after the CCF register is set. 3.2 R e -r e s e t 1. Reset XRST signal. 2. See section 3.1 for registers setting after the procedure of re-reset. 3.3 Software reset 1. Set the value of the SRST register (see section 11.2.1) for re-reset. 2. It is not necessary to reset the CCF register and the MMR register again. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 40 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 4 HOST INTERFACE 4.1 Operation Mode 4.1.1 Host CPU mode Select the host CPU by setting the MODE0 to MODE2 signals as follows: Table 4-1 CPU Type Setting MODE 2 L L L L H L L H H X MODE 1 L H L H X MODE 0 SH3 SH4 V832 SPARClite Reserved CPU 4.1.2 Ready signal mode The MODE2 pin can be used to set the ready signal level when the bus cycle of the host CPU terminates. For the normally not ready mode, set the software wait to 0 or 1 cycles. When using this device in the normally ready mode, set the software wait to 2 cycles. When using this device in the normally not ready mode, set the software wait to one cycle. (When BS_MODE = H three cycles are needed for the , software wait.) The `normally not ready mode' is the mode in which the CORAL XRDY signal is always in the wait state and Ready is returned only when read/write is ready. The `normal ready mode' is the mode in which the CORAL XRDY signal is always in the Ready state and it is put into the wait state only when read/write cannot be performed immediately. Table 4-2 Ready Signal Mode RDY_ MODE L H Ready signal operation Recognizes XRDY signal as `not ready level' and terminates bus cycle (normally not ready mode) Recognizes XRDY signal as `ready level' and terminates bus cycle (normally ready mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 41 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 4.1.3 BS signal mode Connection to a CPU without the BS signal can be made via the BS_MODE signal. This setting can be performed for all CPU modes. To connect to a CPU without the BS signal, set the BS_MODE signal to "High" level. When not using the BS signal, fix the BS pin of CORAL at "High" level. When using the BS_MODE signal as "High" level, with the normally ready mode established, set the CPU software wait to three cycles. Table 4-3 BS_ MODE L H BS Signal Mode Operation of BS signal Connects to CPU with BS signal Connects to CPU without BS signal 4.1.4 Endian CORAL operates in little-endian mode. All the register address descriptions in the specifications are byte address in little endian. When using a big-endian CPU, note that the byte-or word-addresses are different from these descriptions. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 42 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 4.2 Access Mode 4.2.1 SRAM interface Data can be transferred to/from CORAL using SRAM access protocol. CORAL internal registers and graphics memory are all mapped to the physical address area of the host processor. CORAL uses hardware wait based on the XRDY signal, enabling the hardware wait setting of the host CPU. When using the normally not ready mode, set the software wait to "1". When using the normally ready mode, set the software wait to "2". (When using the BS_MODE signal as "High" level, with the normally ready mode established, set the CPU software wait to three cycles.) Switch the ready mode using the RDY_ MODE signal. CPU Read The host processor reads data from internal registers and memory of CORAL in double-word (32 bit) units. Valid data is output continuously while XRD and XCS are being asserted at a "Low" level after XRDY has been asserted. CPU Write The host CPU writes data to internal registers and memory of CORAL in byte, word(16 bit) and double-word( 32 bit) units. 4.2.2 FIFO interface (fixed transfer destination address) This interface transfers display lists stored in host memory. Display list information is transferred efficiently using a single address mode DMA transfer. Data can be transferred to FIFO in relation to FIFO buffer area mapped in memory area using SRAM interface or dual address mode. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 43 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 4.3 DMA Transfer 4.3.1 Data transfer unit DMA transfer is performed in double-word (32 bits) units or 8 double-word (32 bytes) units. Byte and word access is not supported. Note: 8 double-word transfer is supported only in the SH4 mode. 4.3.2 Address mode Dual address mode (mode using ACK) DMA is performed at memory-to-memory transfer between host memory and registers mapped in memory space or graphics memory (destination). Both the host memory address and CORAL is used. In the SH4 mode, the 1 double-word transfer (32 bits) and 8 double-word transfer (32 bytes) can be used. When the CPU transfer destination address is fixed, data can also be transferred to the FIFO interface. However, in this case, even the SH4 mode supports only the 1 double-word transfer. DREQ and DRACK pins and SRAM interface signals are used. In V832, the DREQ, DMAAK, and XTC pins and SRAM interface signals are used. Note: The SH3 mode supports the direct address mode; it does not support the indirect address mode. Dual address mode (mode not using ACK) When not using the ACK signal with the dual address mode established, set bit3 at HostBase+0004h (DNA: Dual address No Ack mode) to 1. When the ACK is not used, the DREQ signal is in the edge mode and the DREQ signal is negated per transfer and then reasserted it in the next cycle. If processing cannot be performed immediately inside CORAL, the DREQ signal remains negated. The transfer count register (DTC) of CORAL is not used, so in order to end DMA transfer, write "1" to the DMA transfer stop register (DTS) from the CPU. Note 1: In the dual DMA mode (mode without ACK), the destination address can be used only for the FIFO. In DMA transfer to the graphics memory, etc., use the dual DMA mode. Note 2: DMA read is not supported. Single address mode (FIFO interface) Data is transferred between host memory (source) and FIFO (destination). Only the address output from the host memory is used, and the data is transferred to the FIFO. This mode does not support data write to the host memory. When the FIFO is full, the DMA transfer is suspended. The 1 double-word transfer (32 bits) and the 8 double-word transfer (32 B) can be used. DREQ, DTACK, and DRACK signal are used. Note: The single-address mode is supported only in the SH4 mode. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 44 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 4.3.3 Bus mode Coral supports the DMA transfer cycle steal mode and burst mode according to setting of external DMA mode. Cycle steal mode (In the V832 mode, the burst mode is called the single transfer mode.) In the cycle steal mode, the right to use the bus is obtained or released at every data transfer of 1 unit. The DMA transfer unit can be selected from between the 1 double-word (32 bits) and 8 double-words (32 B). Burst mode (In the V832 mode, the burst mode is called the demand transfer mode.) When DMA transfer is started, the right to use the bus is acquired and the transfer begins. The data transfer unit can be selected from between the 1 double-word (32 bits) and 8 double-words (32 B). Note: When performing DMA transfer in the dual-address mode, a function for automatically negating DREQ is provided based on the setting of the DBM register. 4.3.4 DMA transfer request Single-address mode DMA is started when the CORAL issues an external request to DMAC of the host processor. Set the transfer count in the transfer count register of the CORAL and then issue DREQ. Fix the CPU destination address to the FIFO address. Dual-address mode DMA is started by two procedures: CORAL issues an external request to DMAC of the host processor, or the CPU itself is started (auto request mode, etc.). n Ack use mode, set the transfer count in the I transfer count register of CORAL and then issue DREQ. Note: In the Ack unused mode and the V832 mode requires no setting of the transfer count register. 4.3.5 Ending DMA transfer * SH3/SH4 When the CORAL transfer count register is set to 0, DMA transfer ends and DREQ is negated. * V832 When the XTC signal from the CPU is low-asserted while the DMAAK signal to S CORAL is high-asserted, the end of DMA transfer is recognized and DREQ is negated. * The end of DMA transfer is detected in two ways: the DMA status register (DST) is polled, and an interrupt to end the drawing command (FD000000H ) is added to the display list and the interrupt is detected. * In the dual address mode (mode not using ACK), the DMA transfer count register (DTC) is not used, so the DMA ending cannot be determined. The DREQ signal can be negated to end DMA by writing 1 from the CPU to the DMA transfer stop register (DTS) of CORAL at DMA transfer end. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 45 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 4.4 Transfer of Local Display List This is the mode in which the CORAL internal bus is used to transfer the display list stored in the graphics memory to the FIFO interface. During transfer of the local display list, the host bus can be used for CPU read/write. How to transfer list: Store the display list in the local memory of CORAL, set the transfer source local address (LSA) and the transfer count (LCO), and then issue a request (LREQ). Whether or not the local display list is currently being transferred is checked using the local transfer status register (LSTA). CPU Host IF FIFO Memory IF SDRAM SDRAM CPU Bus Internal Bus Transfer Path for Local Display List MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 46 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 4.5 Interrupt Coral issues interrupt requests to the host CPU. Following shows the types of interrupt factor and they can be enabled/disabled by IMASK (Interrupt Mask Register). * Vertical synchronization detect * Field synchronization detect * External synchronization error detect * Drawing command error * Drawing command execution end 4.6 SH3 Mode In the SH3 mode, operation is assured under the following conditions: Normally not ready mode * BCLK (CPU bus clock) is 50 MHz or less. * The XWAIT setup time is 9.0 ns or less. Normally ready mode * Three cycles or more are set for the software wait. 4.7 Wait Software wait The software wait is a wait performed on the CPU side; this wait specifies how many cycles of the ready signal (XRDY) sampling timing is ignored. Hardware wait The hardware wait is a wait on the CORAL side that occurs when CORAL itself cannot read/write data immediately. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 47 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 4.8 Memory Map The address is The following shows the memory map of CORAL to the host CPU memory space. mapped differently in SH3, SH4 and V832. 64 MB Space (SH3/SH4) 16 MB Space (V832, SPARClite) 32 MB to 256 KB Graphics memory area 0000000 to 1FBFFFF 16 MB to 256 KB Gr aphics memory area 0000000 to 0FBFFFF 256 KB Register area 1FC0000 to 1FFFFFF 256 KB Register area 0FCFFFF to 0FFFFFF 32 MB Graphics memory area 2000000 to 3FFFFFF Fig. 4.1 Memory Map Table 4-4 Size 32 MB to 256 KB 64 KB 32 KB 32 KB 32 KB 32 KB 32 MB Address Space in SH3/SH4 Mode Resource Base address 00000000 (Name) Host interface registers Display registers Capture registers Drawing registers Geometry engine registers Graphics memory 01FC0000 01FD0000 01FD8000 01FF0000 01FF8000 02000000 (HostBase) (DisplayBase) (CaptureBase) (DrawBase) (GeometryBase) Table 4-5 Size 16 MB to 256 KB 64 KB 32 KB 32 KB 32 KB 32 KB Address Space in V832, SPARClite Mode Resource Base address 00000000 00FC0000 00FD0000 00FD8000 00FF0000 00FF8000 (HostBase) (DisplayBase) (CaptureBase) (DrawBase) (GeometryBase) (Name) Graphics memory Host interface registers Display registers Capture registers Drawing registers Geometry engine registers MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 48 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL When the SH3 or SH4 mode is used, the register area can be moved by writing 1 to bit 0 at HostBase + 005Ch (RSW: Register location Switch). In the initial state, the register space is at the center (1FC0000) of the 64 MB space; access CORAL after about 20 bus clocks after writing 1 to RSW. 64 MB space (SH3/SH4) 32 MB Graphics memory area 0000000 to 1FFFFFF 32 MB to 256 KB Graphics memory area 2000000 to 3FBFFFF 256 KB Register area 3FC0000 to 3FFFFFF Fig. 4.2 Memory Map Table 4-6 Address Mapping in SH3/SH4 Mode Size 64 MB to 256 KB 64 KB 32 KB 32 KB 32 KB 32 KB Resource Graphics memory Host interface registers Display registers Capture registers Drawing registers Geometry engine registers Base address 00000000 03FC0000 03FD0000 03FD8000 03FF0000 03FF8000 (HostBase) (DisplayBase) (CaptureBase) (DrawBase) (GeometryBase) (Name) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 49 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 5 Graphics Memory 5.1 Configuration The Coral uses local external memory (Graphics memory) for drawing and display management. The configuration of this Graphics memory is described as follows: 5.1.1 Data type The Coral handles the following types of data. Display list can be stored in the host (main) memory as well. Texture/tile pattern and text pattern can be defined by a display list as well. Drawing Frame This is a rectangular image data field for 2D/3D drawing. The Coral is able to have plural drawing frames and display a part of these area if it is set to be bigger than display size. The maximum size is 4096x4096 pixel in 32 pixel units. And both indirect color ( 8 bits / pixel) and direct color ( 16 bits / pixel) mode are applicable. Display Frame This is a rectangle picture area for display. The Coral is able to set display layer up to 6 layers. Z Buffer Z buffer is required for eliminating hidden surfaces. In 16 bits modes, 2 bytes and in 8 bits mode, 1 byte are required per 1 pixel. This area has to be cleared before drawing. Polygon Drawing Flag Buffer This area is used for polygon drawing. It is required 1 bit memory area per 1 pixel and 1 x-axis line area both backward and forward of it. This area has to be cleared before drawing. Frame buffer, Z buffer, Displaylist and etc By XRES size Base Address of Polygon Drawing Buffer(PFBR) By drawing frame sizy Polygon drawing flag area => (Y resolution + 2) * X resolution By XRES size Frame buffer, Z buffer, Displaylist and etc Displaylist Buffer The displaylist is a list of drawing commands and parameters. Texture Pattern This pattern is used for texture mapping. The maximum size is up to 4096 x 4096 pixels. Cursor Pattern This is used for hardware cursor. The data format is indirect color ( 8 bits / pixel) mode. And the Coral is able to display two cursor of 64 x 64 pixel size. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 50 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 5.1.2 Memory Mapping A graphics memory is mapped linearly to host CPU address field. Each of these above data is able to be allocated anywhere in the Graphics memory according to the respective register setting. ( However there is some restrictions of an addressing boundary depending on a data type.) 5.1.3 Data Format Direct Color ( 16 bits / pixel ) This data format is described RGB as each 5 bit. Bit15 is used for alpha bit of layer blending. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A R G B Indirect Color ( 8 bits / pixel ) This data format is a color index code for looking up table (palette). 7 6 5 4 3 2 1 0 Color Code Z Value It is possible to use Z value as 8 bits or 16 bits. These data format are unsigned integer. 1 ) 16 bits mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unsigned Integer 2 ) 8 bits mode 7 6 5 4 3 2 1 0 Unsigned Integer Polygon Drawing Flag This data format is 1 bit per 1 pixel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 31 P14 30 P13 29 P12 28 P11 27 P10 26 P9 25 P8 24 P7 23 P6 22 P5 21 P4 20 P3 19 P2 18 P1 17 P0 16 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 51 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Texture / Tile Pattern It is possible to use a pattern as direct color mode ( 16 bits / pixel) or indirect color mode ( 8 bits / pixel). 1 ) Direct color mode ( 16 bits / pixel) This data format is described RGB as each 5 bit. Bit15 is used for alpha bit of stencil or stencil blending. ( Only texture mapping) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A R G B 2) Indirect color mode ( 8 bits / pixel) This data format is a color index code for looking up table (palette). 7 6 5 4 3 2 1 0 Color Code Cursor Pattern This data format is a color index code for looking up table (palette). 7 6 5 4 3 2 1 0 Color Code Video Capture data This data format is Y:Cb:Cr=4:2:2 and 32 bits per 2 pixel. 15 31 14 30 13 29 12 11 10 26 9 25 8 24 7 23 6 22 5 21 4 3 2 18 1 17 0 16 Y0 28 27 20 Cb 19 Y1 Cr Direct Color ( 32 bits / pixel ) This data format is described RGB as each 8 bit. Bit31 is used for alpha bit of layer blending. But the Coral does not support this color mode drawing. Therefore please draw this layer by CPU writing. 15 31 14 30 13 29 12 11 10 26 9 25 8 24 7 23 6 22 5 21 4 3 2 18 1 17 0 16 G 28 27 20 B 19 A Reserved R MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 52 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 5.2 Frame Management 5.2.1 Single Buffer The entire or partial area of the drawing frame is assigned as a display frame. The display field is scrolled by relocating the position of the display frame. When the display frame crosses the border of the drawing frame, the other side of the drawing frame is displayed, assuming that the drawing frame is rolled over (top and left edges assumed logically connected to bottom and right edges, respectively). To avoid the affect of drawing on display, the drawing data can be transferred to the Graphics Memory in the blanking time period. 5.2.2 Double Buffer Two drawing frames are set. While one frame is d isplayed, drawing is done at the other frame. Flicker-less animation can be performed by flipping these two frames back and forth. Flipping is done in the blanking time period. There are two flipping modes: automatically at every scan frame period, and by user control. The double buffer is assigned independently for the L2, L3, L4, L5 layers. 5.3 Memory Access 5.3.1 Memory Access by host CPU Graphics memory is mapped linearly to host CPU address field. The host CPU can access the Graphics memory like a SRAM. 5.3.2 Priority of memory accessing The priority of Graphics memory accessing is the follows: 1. 2. 3. 4. 5. Refresh Video Capture Display processing Host CPU accessing Drawing accessing MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 53 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 5.4 Connection with memory 5.4.1 Connection with memory The memory controller of Coral supports simple connection with SD/FCRAM by setting MMR(Memory Mode Register). If there is N(=11 to 13) address pins in SD/FCRAM, please connect the SD/FCRAM address(A[n]) pin to the Coral's memory address(MA[n]) pin and SD/FCRAM bank pin to the Coral's next address(MA[N]) pin. Then please set MMR by a number and type of memory. The follows are the connection table between Coral pin and SD/FCRAM pin. 64M bit SDRAM(x16 bit) Coral pins SDRAM pins MA[11:0] MA12 MA13 A[11:0] BA0 BA1 64M bit SDRAM(x32 bit) Coral pins SDRAM pins MA[10:0] MA11 MA12 A[10:0] BA0 BA1 128M bit SDRAM(x16 bit) Coral pins SDRAM pins MA[11:0] MA12 MA13 A[11:0] BA0 BA1 128M bit SDRAM(x32 bit) Coral pins SDRAM pins MA[11:0] MA12 MA13 A[11:0] BA0 BA1 256M bit SDRAM(x16 bit) Coral pins SDRAM pins MA[12:0] MA13 MA14 A[12:0] BA0 BA1 16M bit FCRAM(x16 bit) Coral pins FCRAM pins MA[10:0] MA11 A[10:0] BA MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 54 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6 DISPLAY CONTROLLER 6.1 Overview Display control Window display can be performed for six layers. Window scrolling, etc., can also be performed. Backward compatibility Backward compatibility with previous products is supported in the four-layer display mode or in the left/right split display mode. Video timing generator The video display timing is generated according to the display resolution (from 320 x 240 to 1024 x 768). Color look-up There are two sets of color look-up tables by palette RAM for the indirect color mode (8 bits/pixel). Cursor Two sets of hardware cursor patterns (8 bits/pixel, 64 x 64 pixels each) can be used. 6.2 Display Function 6.2.1 Layer configuration Six-layer window display is performed. Layer overlay sequence can be set in any order. A four-layer display mode and left/right split display mode are also provided, supporting backward compatibility with previous products. L0 ( L0WX,L0WY) L5 ( L5WX,L5WY) L4 ( L4WX,L4WY) L2 ( L2WX,L2WY) L1 ( L1WX,L1WY) L0,L2,L4 (0,0 ) L1 ( WX,WY) L3,L5 (HDB+1,0) L3 ( L3WX,L3WY) background color (a) Six layerd window display (b) Four layered display for downward compatibility MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 55 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Configuration of Display Layers The correspondence between the display layers for this product and for previous products is shown below. Layer correspondence L0 L1 L2 L3 L4 L5 C W ML MR BL BR Coordinates of starting point Window mode (L0WX, L0WY) (L1WX, L1WY) (L2WX, L2WY) (L3WX, L3WY) (L4WX, L4WY) (L5WX, L5WY) Compatibility mode (0, 0) (WX, WY) (0, 0) (HDB, 0) (0, 0) (HDB, 0) Width/height Window mode (L0WW, L0WH + 1) (L1WW, L1WH + 1) (L2WW, L2WH + 1) (L3WW, L3WH + 1) (L4WW, L4WH + 1) (L5WW, L5WH + 1) Compatibility mode (HDP + 1, VDP + 1) (WW, WH + 1) (HDB + 1, VDP + 1) (HDP - HDB, VDP + 1) (HDB + 1, VDP + 1) (HDP - HDB, VDP + 1) C, W, ML, MR, BL, and BR above mean layers for previous products. The window mode or the compatibility mode can be selected for each layer. It is possible to use new functions through minor program changes by allowing the coexistence of display modes instead of separating them completely. However, if high resolutions are displayed, the count of layers that can be displayed simultaneously and pixel data may be restricted according to the graphics memory ability to supply data. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 56 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6.2.2 Overlay (1) Overview Image data for the six layers (L0 to L5) is processed as shown below. L0(C) data Cursor0 data Cursor1 data L1(W) data Overlay L2(ML) data L3(MR) data L4(BL) data L5(BR) data L2 data Pallet-0 Pallet-1 Layer Selector Blender YUV/RGB Pallet-2 L3 data Pallet-3 L4 data L5 data The fundamental flow is: Palette Layer selection Blending. The palettes convert 8 -bit color codes to the RGB format. The layer selector exchanges the layer overlay sequence arbitrarily. The blender performs blending using the blend coefficient defined for each layer or overlays in accordance with the transparent-color definition. The L0 layer corresponds to the C layer for previous products and shares the palettes with the cursor. As a result, the L0 layer and cursor are overlaid before blend operation. The L1 layer corresponds to the W layer for previous products. To implement backward compatibility with previous products, the L1 layer and lower layers are overlaid before blend operation. The L2 to L5 layers have two paths; in one path, these layers are input to the blender separately and in the other, these layers and the L1 layer are overlaid and then are input to the blender. When performing processing using the extended mode, select the former; when performing the same processing as previous products, select the latter. It is possible to specify which one to select for each layer. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 57 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL (2) Overlay mode Image layer overlay is performed in two modes: simple priority mode, and blend mode. In the simple priority mode, processing is performed according to the transparent color defined for each layer. When the color is a transparent color, the value of the lower layer is used as the image value for the next stage; when the color is not a transparent color, the value of the layer is used as the image value for the next stage. Dview = Dnew (when Dnew does not match transparent color) = Dlower (when Dnew matches transparent color) When the L1 layer is in the YCbCr mode, transparent color checking is not performed for the L1 layer; processing is always performed assuming that transparent color is not used. In the blend mode, the blend ratio "r" defined for each layer is specified using 8-bit tolerance, and the following operation is performed: Dv iew = Dnew*r + Dlower*(1 - r) Blending is enabled for each layer by mode setting and a specific bit of the pixel is set to "1". For 8 bits/pixel, the MSB of RAM data enables blending; for 16 bits/pixel, the MSB of data of the relevant layer enables blending; for 24 bits/pixel, the MSB of the word enables blending. (3) Blend coefficient layer In the normal blend mode, the blend coefficient is fixed for each layer. However, in the blend coefficient layer mode, the L5 layer can be used as the blend coefficient layer. In this mode, the blend coefficient can be specified for each pixel, providing gradation, for example. When using this mode, set the L5 layer(L5M and L5EM register) to 8 bits/pixel, window display mode and extend overlay mode. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 58 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6.2.3 Display parameters The display area is defined according to the following parameters. Each parameter is set independently at the respective register. HTP HSP HDP HDB HSW LnWY VDP LnWX VSP LnWW LnWH VTR VSW Fig. 5.1 Display Parameters Note: The actual parameter settings are little different from the above. The details, please refer "11.3.1 Interlaced mode". HTP HSP HSW HDP HDB VTR VSP VSW VDP LnWX LnWY LnWW LnWH Horizontal Total Pixels Horizontal Synchronize pulse Position Horizontal Synchronize pulse Width Horizontal Display Period Horizontal Display Boundary Vertical Total Raster Vertical Synchronize pulse Position Vertical Synchronize pulse Width Vertical Display Period Layer n Window position X Layer n Window position Y Layer n Window Width Layer n Window Height When not splitting the window, set HDP to HDB and display only the left side of the window. The settings must meet the following relationship: 0 < HDB HDP < HSP < HSP + HSW + 1 < HTP 0 < VDP < VSP < VSP + VSW + 1 < VTR MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 59 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6.2.4 Display position control The graphic image data to be displayed is located in the logical 2D coordinates space (logical graphics space) in the Graphics Memory. There are six logical graphics spaces as follows: * L0 layer * L1 layer * L2 layer * L3 layer * L4 layer * L5 layer The relation between the logical graphics space and display position is defined as follows: Origin Address (OA) Stride (W) Display Address (DA) Display Position X,Y (DX,DY) Logical Frame Height (H) Display Frame VDP HDP Fig. 5.2 Display Position Parameters OA W H DA DX DY Origin Address Stride Height Display Address Display Position Origin address of logical graphics space. Memory address of top left edge pixel in logical frame origin Width of logical graphics space. Defined in 64-byte unit Height of logical graphics space. Total raster (pixel) count of field Display origin address. Top left position address of display frame origin Display origin coordinates. Coordinates in logical frame space of display frame origin MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 60 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Coral scans the logical graphics space as if the entire space is rolled over in both the horizontal and vertical directions. Using this function, if the display frame crosses the border of the logical graphics space, the part outside the border is covered with the other side of the logical graphics space, which is assumed to be connected cyclically as shown below: Logical Frame Origin 64 w Additionally drawn area L Previous display origin New display origin Fig. 5.3 Wrap Around of Display Frame The expression of the X and Y coordinates in the frame and their corresponding linear addresses (in bytes) is shown below. A(x,y) = x x bpp/8 + 64wy (bpp = 8 or 16) The origin of the displayed coordinates has to be within the frame. To be more specific, the parameters are subject to the following constraints: 0 DX < w x 64 x 8/bpp (bpp = 8 or 16) 0 DY < H DX, DY, and DA have to indicate the same point within the frame. In short, the following relationship must be satisfied. DA = OA + DX x bpp/8 + 64w x DY (bpp = 8 or 16) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 61 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6.3 D i s p la y C o l o r Color data is displayed in the following modes: Indirect color (8 bits/pixel) In this mode, the index of the palette RAM is displayed. Data is converted to image data consisting of 6 bits for R, G, and B via the palette RAM and is then displayed. Direct color (16 bits/pixel) Each level of R, G, and B is represented using 5 bits. Direct color (24 bits/pixel) Each level of R, G, and B is represented using 8 bits. YCbCr color (16 bits/pixel) In this mode, image data is displayed with YCbCr = 4:2:2. Data is converted to image data consisting of 8 bits for R, G, and B using the operation circuit and is then displayed. The display colors for each layer are shown below. Layer L0 L1 L2 L3 L4 L5 Compatibility mode Direct color (16, 24), Indirect color (P0) Direct color (16, 24), Indirect color (P1), YCbCr Direct color (16, 24), Indirect color (P1) Direct color (16, 24), Indirect color (P1) Direct color (16, 24), Indirect color (P1) Direct color (16, 24), Indirect color (P1) Extended mode Direct color (16, 24), Indirect color (P0) Direct color (16, 24), Indirect color (P1), YCbCr Direct color (16, 24), Indirect color (P2) Direct color (16, 24), Indirect color (P3) Direct color (16, 24) Direct color (16, 24) "Pn" stands for the corresponding palette RAM. Four palettes are used as follows: Palette 0 (P0) This palette corresponds to the C-layer palette for previous products. This palette is used for the L0 layer. This palette can also be used for the cursor. Palette 1 (P1) This palette corresponds to the M/B layer palette for previous products. In the compatibility mode, this palette is common to layers L1 to 5. In the extended mode, this palette is dedicated to the L1 layer. Palette 2 (P2) This palette is dedicated to the L2 layer. This palette can be used only for the extended mode. Palette 3 (P3) This palette is dedicated to the L2 layer. This palette can be used only for the extended mode. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 62 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6.4 Cursor 6.4.1 Cursor display function CORAL can display two hardware cursors. Each cursor is specified as 64 x 64 pixels, and the cursor pattern is set in the Graphics Memory. The indirect color mode (8 bits/pixel) is used and the L0 layer palette is used. However, transparent color control (handling of transparent color code and code 0) is independent of L0 layer. Blending with lower layer is not performed. 6.4.2 Cursor control The display priority for hardware cursors is programmable. The cursor can be displayed either on upper or lower the L0 layer using this feature. A separate setting can be made for each hardware cursor. If part of a hardware cursor crosses the display frame border, the part outside the border is not shown. Usually, cursor 0 is preferred to cursor 1. However, with cursor 1 displayed upper the L0 layer and cursor 0 displayed lower the L0 layer, the cursor 1 display is preferred to the cursor 0. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 63 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6.5 Display Scan Control 6.5.1 Applicable display The following table shows typical display resolutions and their synchronous signal frequencies. The pixel clock frequency is determined by setting the division r te of the display reference clock. The display a reference clock is either the internal PLL (400.9 MHz at input frequency of 14.318 MHz), or the clock supplied to the DCLKI input pin. The following table gives the clock division rate used when the internal PLL is the display reference clock: Table 4-1 Resolution 320 x 240 400 x 240 480 x 240 640 x 480 854 x 480 800 x 600 1024 x 768 Division rate of reference clock 1/60 1/48 1/40 1/16 1/12 1/10 1/6 Resolution and Display Frequency Horizontal total pixel count 424 530 636 800 1062 1056 1389 Horizontal frequency 15.76 kHz 15.76 kHz 15.76 kHz 31.5 kHz 31.3 kHz 38.0 kHz 48.1 kHz Vertical total raster count 263 263 263 525 525 633 806 Vertical frequency 59.9 Hz 59.9 Hz 59.9 Hz 59.7 Hz 59.9 Hz 60.0 Hz 59.9 Hz Pixel frequency 6.7 MHz 8.4 MHz 10.0 MHz 25.1 MHz 33.4 MHz 40.1 MHz 66.8 MHz Pixel frequency = 14.318 MHz x 28 x reference clock division rate (when internal PLL selected) = DCLKI input frequency x reference clock division rate (when DCLKI selected) Horizontal frequency = Pixel frequency/Horizontal total pixel count Vertical frequency = Horizontal frequency/Vertical total raster count MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 64 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6.5.2 Interlace display CORAL can perform both a non-interlace display and an interlace display. When the DCM register synchronization mode is set to interlace video (11), images in memory are output in odd and even rasters alternately to each field, and one frame (odd + even fields) forms one screen. When the DCM register synchronization mode is set to interlace (10), images in memory are output in raster order. The same image data is output to odd fields and even fields. Consequently, the count of rasters on the screen is half of that of interlace video. However, unlike the non-interlace mode, there is a distinction between odd and even fields depending on the phase relationship between the horizontal and vertical synchronous signals. Odd Eve n Non-Interlace Interlace Video Interlace Fig. 5.4 Display Difference between Synchronization Modes MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 65 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6.6 The external synchronous signal The display scan can be performed by synchronizing horizontal/vertical synchronous signal from the external. In selecting the external synchronization mode, Coral is sampling the HSYNC signal and displays the synchronizing the external video signal. Either the internal PLL clock or the DCL KI input signal could be selected for the sampling clock. Also, the superimposed analog output is performed by the chroma key process. The following diagram shows an example of the external synchronization circuit. External Sync Enable Hsync In Vsync In 3 states buffer ESY bit HSYNC VSYNC L0 L1 L2 L3 L4 L5 Cursor 0 Cursor 1 Display Timming Generator Digital RGB Out Overlap L0 Hsync Out Vsync Out CORAL CKM bit KEYC register Compare GV Latency compensation for DAC D-FFs Analo g RGB In Video SW (Pedestal Clump Input) Superimposed Analog RGB Out An example of the external synchronization circuit The external synchronization mode is performed by setting the ESY bit of the DCM register. In setting the external synchronization mode, HSYNC, VSYNC, and EO pin of Coral is changed to the input mode. After that it needs to be provided the synchronous signal by using the 3 state buffer from the external. When turning off the external synchronization mode, Coral internal ESY bit needs to be switched OFF after disconnecting the synchronous input signal from the external. The buffer of the external synchronization signal must not be switched ON when the synchronous output signal of Coral is ON. Follow the previous instruction to prevent simultaneous ON from occurring. In using the external synchronous signal with the display clock based on the internal PLL, Coral extends the clock period and fits the clock phase with the horizontal synchronous signal phase after inputting the horizontal synchronous pulse. The following caution is necessary. In case of connecting the high speed transmit signal, such as LVDS, with the digital RGB output, PLL with a built-in the high speed serial transmission is temporally unstable due to this connection. Therefore, MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 66 DAC FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL the external synchronous signal based on the internal PLL must not be used with high speed synchronous transmit signal. The synchronization of the horizontal direction is controlled by the following state diagram. otherwise otherwise Disp The horizontal resolution counter = HDP The horizontal resolution Fporch The horizontal resolution counter = HTP detecting the external horizontal synchronous signal or the horizontal synchronous pulse counter = HSW Bporch otherw i s e When the horizontal resolution counter matches the HTP, it is initialized. Sync otherwise The horizontal resolution counter is is halted, starts to count the horizontal synchronous pulse counter. The finite state diagram is controlled by the horizontal resolution counter. The period of outputting the signal is assigned the Disp state. When the value of the horizontal resolution counter matches that of the HDP register, it ends to output the signal and the current state is transmitted from Disp state to Fporch state (front porch). In the Fporch state, when the value of the vertical resolution register matches that of the HSP register, the current state is transmitted to the Sync state. In this state, it waits for the horizontal synchronous signal from the external. Coral detects the negative edge of the horizontal synchronous pulse from the external and synchronizes it. In detecting the horizontal synchronous signal from the external, the current state is transmitted to the Bporch state (back porch). The horizontal resolution register does not count in the Sync state, instead the horizontal synchronous counter is incremented from zero. When the value of this counter matches the setting value of the HSW register, the current state is transmitted to the Bporch state without detecting the horizontal synchronous signal form the external. When the value of the horizontal resolution counter matches that of the HTP register in the Bporch state, the horizontal resolution counter is reset, and also the current state is transmitted to the Disp state and it begins to display the next cluster. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 67 counter = HSP FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL The synchronization of vertical direction is controlled by the following state diagram. otherwise otherwise Disp The cluster counte r = V D P Fporch detecting the external vertical synchronous pulse to be asserted The cluster counter = VTR detecting the negative edge of the external vertical synchronous pulse Bporch otherwise When the cluster counter matches the VTP, it is initialized. Sync otherwise The state diagram of the vertical direction is controlled by the value of the cluster counter. The period of outputting the signal is assigned the Disp state. When the value of the cluster counter matches the value of the VDP register, it ends to output the signal and the current state is transmitted from the Disp state to the Fporch state. In the Fporch state, it waits the external synchronous pulse to be asserted. In detecting the external synchronous pulse to be asserted, the current state is transmitted to the Sync state. In the Sync state, it waits for the negative edge of the external synchronous signal. In detecting the negative edge, the current state is transmitted to the Bporch state. When the value of the cluster counter matches the values of the VTR register, the cluster counter is reset, and also the current state is transmitted to the Disp state and it starts to display the next field. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 68 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 6.7 Video Interface, NTSC/PAL Output In outputting NTSC/PAL signal, NTSC/PAL encoder must be connected externally as shown below: CORAL AOUTR AOUTG AOUTB NTSC Encoder R-IN G-IN B-IN VIDEO-OUT CSYNC CLK 1/4 CSYNC-IN Fsc-IN 14.318 MHz Fig. 5.4 Example of NTSC Encoder Connection MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 69 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 7 Video Capture 7.1 Format 7.1.1 Input Data Format Input a digital video stream in the ITU RBT-656 format. NTSC and PAL signals are both supported. 7.1.2 Video Signal Capture When the VIE bit of the video capture mode register (VCM) is 1, Coral is enabled to capture video stream data from the 8-bit VI pin in synchronization with the CCLK clock. Only a digital video stream conforming to ITU -RBT656 can be processed. For this reason, a Y,Cb,Cr 4:2:2 format to which timing reference codes are added is used. The video stream is captured according to the timing reference codes; Coral automatically supports both NTSC and PAL. However, to detect error codes, set NTSC/PAL in the VS bit of VCM. If NTSC is not set, reference the number of data in the capture data count register (CDCN). If PAL is not set, reference the number of data in the capture data counter register (CDCP). If the reference data does not match the stream data, bit 4 to bit 0 of the video capture status register (VCS) will be values other than 0000. 7.1.3 Non-interlace Transformation Captured video graphics can be displayed in non-interlaced format. Two modes (BOB and WEAVE) can be selected at non-interlace transformation. - BOB Mode In odd fields, the even-field rasters generated by average interpolation are added to produce one frame. In even fields, the odd-field rasters generated by average interpolation are added to produce one frame. The BOB mode is selected by enabling vertical interpolation with the VI bit of the video capture mode register (VCM) and setting the L1IM bit of the L1-layer mode register (L1M) to 0. - WEAVE Mode Odd and even fields are merged in the video capture buffer to produce one frame. Vertical resolutions in the WEAVE mode are higher than those in the BOB mode but raster dislocation appears at moving places. The WEAVE mode is selected by disabling vertical interpolation with the VI bit of VCM and setting the L1IM bit of L1-layer mode register(L1M) to 1. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 70 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 7.2 Video Buffer 7.2.1 Data Format Captured graphics are stored in memory in the 16-bit/pixel YcbCr format. Video data is transformed to the RGB format when it is displayed in the L1-layer. 31 Y1 24 23 Cr 16 15 Y0 87 Cb 0 7 6 5 4 3 2 1 0 Y0,Y1 Cr,Cb Y7 C7 Y6 C6 Y5 C5 Y4 C4 Y3 C3 Y2 C2 Y1 C1 Y0 C0 7.2.2 Synchronous Control Video graphics data is written to scan-independent memory for display. Memory for video capture is controlled by the ring buffer method. When graphics data for one frame is ready in memory, the frame is displayed. If the video capture frame rate is different from the display frame rate, a frame is omitted or the same frame is displayed continuously. 7.2.3 Area Allocation Allocate an area of about 2.2 frames to the video capture buffer. The size of this area is equivalent to the size that considers the margin equivalent to the double buffer of the frame. Set the starting address and upper-limit address of the area in the CBOA/CBLA registers. Here, specify the raster start position as the upper-limit address. To allocate n rasters as the video capture buffer, set the upper-limit value as follows: CBLA = CBOA + 64n X CBS If CBLA does not match the head of a raster, video capture data is written beyond the upper limit by only 1 raster (max.). Note that if other meaningful data is held in the area, the user-intended operation is hindered by overwriting. For reduced display, allocate the buffer area of the reduced frame size. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 71 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 7.2.4 Window Display The L1 layer is used to display the captured video graphics. graphics can be displayed as the full screen or as a window. A part or the whole o the captured f To capture and display video graphics, set the L1 layer to the capture synchronous mode (L1CS = 1). In the capture synchronous mode, the L1 layer displays the latest frame in the video capture buffer. The display addresses used in the normal mode are ignored. The stride of the L1 layer must match that of the video capture buffer. displayed graphics have oblique distortion. If they do not match, the Match the display size of the L1 layer with the reducted graphics size of the video capture. Setting the display size of the L1 layer larger than the capture image size causes display of invalid data. The L1 layer supports selection of the RGB display format and YcbCr display format. To capture video graphics, select the YcbCr display format (WYC = 1). 7.2.5 Interlace Display The graphics captured in the video capture buffer in the WEAVE mode can be displayed in interlace. Interlace display setting is the same as WEAVE mode setting. Select `Interlace & video display' for display scan. Flicker appears in moving video graphics. To prevent flicker, set the OO (Odd Only) bit of the capture buffer mode register (CBM) to "1". MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 72 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 7.3 Scaling 7.3.1 Video Reduction Function When the CM bits of the video capture mode register (VCM) are 11, Coral reduces the video screen size. The reduction can be set independently in the vertical and horizontal scales. The reduction is set per line in the vertical direction and in 2-pixel units in the horizontal direction. The scale setting value is defined by an input/output value. It is a 16-bit fixed fraction where the integer is represented by 5 bits and the fraction is represented by 11 bits. Valid setting values are from 0800H to FFFFH. Set the vertical direction at bit 31 to bit 16 of the capture scale register (CSC) and the horizontal direction at bits 15 to bit 00. The initial value for this register is 08000800H (once). An example of the expressions for setting a reduction in the vertical and horizontal directions is shown below. 576 490 lines 1.176x2048=2408 Reduction in horizontal direction 720 648 pixels 1.111x2048=2275 Therefore, 096808E3H is set in CSC. The capture horizontal pixel register (CHP) and capture vertical pixel register (CVP) are used to limit the number of pixels processed during scaling. They are not used to set scaling values. Clamp processing is performed on the video streaming data outside the values set in CHP and CVP. Usually, the defaults for these registers are used. Reduction in vertical direction 576/490 = 1.176 0968H 720/648 = 1.111 08E3H 7.3.2 Vertical Interpolation When the VI bit of the video capture mode register (VCM) is "0", data in the same field is used to interpolate the interlace screen vertically. The interlace screen is doubled in the vertical direction. When the VI bit is "1", the interlace screen is not interpolated vertically. 7.4 Error Handling 7.4.1 Error Detection Function If an expected control code is not detected in the input video stream, an error occurs. If an error occurs, the status is returned to the register. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 73 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 8 GEOMETRY ENGINE 8.1 Geometry Pipeline 8.1.1 Processing flow The flow of geometry is shown below. Object coordinates (OC) MVP Transformation Clip coordinates (CC) Clipping Back face carling 3D-2D Transformation Normalized device coordinates (NDC) View port transformation Drawing (device) coordinates (DC) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 74 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 8.1.2 Model-view-projection transformation) (MVP) transformation (OCCC coordinate The geometry engine transforms the vertex of the "OC" coordinate system specified by the G_Vertex packet to the "CC" coordinate system according to the coordinate transformation matrix (OC CC Matrix) specified by the G_LoadMatrix packet. The "OC CC Matrix" is a "4 x 4" matrix consisting of a ModelView matrix and a Projection matrix. If "Zoc" is not contained in the input parameter of the G_Vertex packet (Z-bit of GMDR0 is off), (OC CC) coordinate transformation is processed as "Zoc = 0". When GMDR0[0] is 0 (orthogonal projection transformation), OC CC coordinate transformation is processed as "Wcc = 1.0". OC: Object Coordinates CC: Clip Coordinates Xcc Ycc Zcc Wcc Ma0 Ma1 Mb1 Mc1 Md1 Ma2 Mb2 Mc2 Md2 Ma3 Mb3 Mc3 Md3 Xoc Yoc Zoc 1 = Mb0 Mc0 Md0 Ma0 to Md3: OC CC Matrix Xoc to Zoc: X, Y, and Z of OC coordinate system Xcc to Woc: X, Y, Z, and W of CC coordinate system 8.1.3 3D-2D transformation (CCNDC coordinate transformation) The geometry engine divides "XYZ" of the "CC" coordinate system by "Wcc" (Perspective Division). NDC: Normalized Device Coordinates Xndc Yndc Zndc Xcc = 1/Wcc Ycc Zcc Xndc to Zndc: X, Y, and Z of "NDC" coordinate system MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 75 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 8.1.4 View port transformation (NDCDC coordinate transformation) The geometry engine transforms "XYZ" of the "NDC" coordinate system to the "DC" coordinate system according to the transformation coefficient specified by G_ViewPort and G_DepthRange. "X_Scaling,X_Offset" and "Y_Scaling,Y_Offset" are coefficients to be mapped finally to Frame Buffer. Xdc and Ydc must be included within the drawing input range (-4096 to 4095). "Z_Scaling" and "Z_Offset" are coefficients to be mapped finally to "Z Buffer". "Zdc" must be included within the "Z Buffer" range (0 to 65535). DC: Device Coordinates Xdc = X_Scaling*Xndc + X_Offset Ydc = Y_Scaling*Yndc + Y_Offset Zdc = Z_Scaling*Zndc + Z_Offset 8.1.5 View volume clipping Expression for determination The expression for determining the CORAL view volume clipping is shown below. intended to prevent the overflow caused by 1/W. Xmin*Wcc Xcc Xmax*Wcc Ymin*Wcc Ycc Ymax*Wcc Zmin*Wcc Zcc Zmax*Wcc Wmin Wcc Note: Xmin, Xmax, Ymin, Ymax, Zmin, Zmax, and Wmin are the clip boundary values set by the G_ViewVolumeXYClip/ZClip/WClip packet. W clipping is Clipping-on/-off View volume clipping-on/-off can be switched by using the clip boundary values set by the G_ViewVolumeXYClip/Zclip/WClip packet. To switch view volume clipping to off, set the maximum and minimum values of the geometry data format (IEEE single-precision floating point(*1)) in the "Clip.max" value(*2) and "Clip.min" value(*3), respectively. In this case, `All coordinate transformation results' can be evaluated as within view volume range, making it possible to obtain the effect of view volume clipping-off. This method is valid only when W clipping does not occur. When a clip boundary value (Wmin) that causes W clipping to occur is set, clipping is also performed for each clip area. Consequently, set an appropriate clip boundary value for Clip. Max value. and Clip. Min value., respectively. If other values are set in "Clip.max" and Clip.min, view volume clipping-on operates. The coordinate transformation result is always compared with the values set in "Clip.max" and "Clip.min". *1: Maximum value = 0x7f7fffff, minimum value = 0xff7fffff *2: Xmin,Ymin, Zmin, Wmin *3: Xmax, Ymax, Zmax MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 76 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL An example of the G_ViewVolumeZclip packet is shown below. 0xf1012010 //Setting of GMDR0 0x00000000 //Data format: Floating point data format 0x45000000 //G_ViewVolumeZclip packet 0xff7fffff //Zmin.float setting value (minimum value of IEEE single-precision floating point) 0x7f7fffff //Zmax.float setting value (maximum value of IEEE single-precision floating point) Example of G_ViewVolumeZclip Packet when Z Clipping Off "W" clipping at orthogonal projection transformation "W" at orthogonal projection transformation (GMDR0[0] = 0) is treated as "Wcc=1.0". For this reason, to suppress "W" clipping, the set "Wmin" value must be larger than 0 and 1.0 or less. Relationship with drawing clip frame For the following reasons, the clip boundary values of the view volume should be set so that the values after DC coordinate transformation will be larger than the drawing clip frame (2 pixels or more). (1) "XY" on the view volume clip frame of the "CC" coordinate system may be drawn one pixel outside or inside the frame due to an operation error when it is finally mapped to the "DC" coordinate system. (2) When the end point of a line overlaps the view volume frame mapped to the "DC" coordinate system, there are two cases, where the dots on the frame are drawn, and not drawn depending on the specifying of the line drawing attribute (end point drawing/non-drawing). (3) When the start point of a line overlaps the view volume frame mapped to the "DC" coordinate system, the dots on the frame are always drawn. When the line drawing attribute is `end point non-drawing,' the dots on the frame are drawn at the starting point, but they may not be drawn at the end point. (4) When applying to triangle and polygon drawing the rasterizing rule `dots containing center of pixel drawn. Dots on right side and base of triangle not drawn.' depending on the value of the fraction, a gap may be produced between the right side and base of the frame. "DC" Coordinates image of view volume clip frame Drawing area Drawing clip frame A space of two pixels or more is required. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 77 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 8.1.6 Back face curling In CORAL, a triangle direction can be defined and a mode in which drawing for the back face is inhibited (back face carling) is supported. The on/off operation is controlled by the GMDR2[0] setting. GMDR2[0] must be set to 1 only when back face carling is required. When back face carling is not required such as in `line,' `point,' and `polygon primitive,' GMDR2[0] must be set to 0. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 78 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 8.2 Data Format 8.2.1 Data format The supported data formats are 32-bit single-precision floating-point format, 32-bit fixed-point format, integer packed format, and RGB packed format. All internal processing is performed in the floating-point format. For this reason, the integer packed format, fixed-point format, and RGB packed format must be converted to the floating-point format. The processing speeds in these formats are slightly lower than in the 32-bit single-precision floating-point format. The data format to use is selected by setting the GMDR0 register. (1) 32-bit single-precision floating-point format 31 30 s e 23 22 f 0 s: Sign bit (1 bit) e: Exponent part (8 bits) f: Mantissa (23 bits): `1.f' shows the fraction. `1' is a hidden bit. The numerical value of the floating-point format becomes (-1) (1.f)2 (2) Signed fixed-point format (SFIX16.16) 31 30 s Int s (e-127) (0 < e < 255). 16 15 Frac 0 s: Sign bit (1 bit) int: Integer (15 bits) frac: Fraction (16 bits) (3) Signed integer packed format (SINT16.SINT16) 31 30 s Y.int 16 15 14 s X.int 0 s: Sign bit (1 bit) int: Integer (15 bits) (4) RGB packed format 31 reserved 24 23 R 16 15 G 87 B 0 R, G, B: Color bits (8 bits) (5) ARGB packed format 31 A 24 23 R 16 15 G 87 B 0 A: Alpha bits (8 bits) R, G, B: Color bits (8 bits) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 79 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 8.3 Setup Engine 8.3.1 Setup processing The vertex data transformed by the geometry engine is transferred to the setup engine. CORAL has a drawing interface that is compatible with the MB86290A. It operates parameters for various slope calculations, etc., with the setup engine. When the obtained parameters are set in the drawing engine, the final drawing processing starts. 8.4 Log Output of Device Coordinates A function is provided to output device coordinates (DC) data obtained by view port conversion to local memory (graphics memory). 8.4.1 Log output mode Drawing & log output command Log output of drawing coordinates (device coordinates) can be performed concurrently with primitive drawing. Log output can be controlled using the command with log output on/off attribute; log output is performed only when the log output on attribute is specified. Log output dedicated command When the log output dedicated command is used, log output of the device coordinates can be performed. 8.4.2 Log output destination address The log output destination address is controlled by the device coordinates log pointer. Once set an address, this pointer automatically increment an output address. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 80 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9 DRAWING PROCESSING 9.1 Coordinate System 9.1.1 Drawing coordinates After the calculation of coordinates by the geometry engine, CORAL draws data in the drawing frame in the graphics memory that finally uses the drawing coordinates (device coordinates). Drawing frame is treated as 2D coordinates with the origin at the top left as shown in the figure below. The maximum coordinates is 4096 x 4096. Each drawing frame is located in the G raphics Memory by setting the address of the origin and resolution of X direction (size). Although the size of Y direction does not need to be set, Y coordinates which are max. at drawing must not be overlapped with other area. In addition, at drawing, s pecifying the clip frame (top left and bottom right coordinates) can prevent the drawing of images outside the clip frame. X (max. 4096) Origin Drawing frame size X Drawing frame size Y (Xmin, Ymin) Clip frame Y (max. 4096) (Xmax, Ymax) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 81 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.1.2 Texture coordinates Texture coordinate is a 2D coordinate system represented as S and T (S: horizontal, T: vertical). Any integer in a range of -8192 to +8191 can be used as the S and T coordinates. The texture coordinates is correlated to the 2D coordinates of a vertex. One texture pattern can be applied to up to 4096 x 4096 pixels. The pattern size is set in the register. When the S and T coordinates exceed the maximum pattern size, the repeat, cramp or border color option is selected. S (max. 8192) T (max. 8192) max. 4096 pixels Texture pattern MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 82 max. 4096 pixels Origin FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.1.3 Frame buffer For drawing, the following area must be assigned to the Graphics Memory. The frame size ( count of pixels on X direction) is common for these areas. Drawing frame The results of drawing are stored in the graphical image data area. Both the direct and indirect color mode are applicable. Z buffer Z buffer is required for eliminating hidden surfaces. In 16 bits mode, 2 bytes and in 8 bits mode, 1 byte are required per 1 pixel. Polygon drawing flag buffer This area is used for polygon drawing. 1bit is required per 1 pixel. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 83 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.2 Figure Drawing 9.2.1 Drawing primitives CORAL has a drawing interface that is compatible with the MB86290A graphics controller which does not perform geometry processing. The following types of figure drawing primitives are compatible with the MB86290A. * Point * Line * Triangle * High-speed 2DLine * High-speed 2DTriangle * Polygon 9.2.2 Polygon drawing function An irregular polygon (including concave shape) is drawn by hardware in the following manner: 1. Execute PolygonBegin command. Initialize polygon drawing hardware. 2. Draw vertices. Draw outline of polygon and plot all vertices to polygon draw flag buffer using high-speed 2DTriangle primitive. 3. Execute PolygonEnd command. Copy shape in polygon draw flag buffer to drawing frame and fill shape with color or specified tiling pattern. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 84 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.2.3 Drawing parameters The MB86290A-compatible interface uses the following parameters for drawing: The triangles (Right triangle and Left triangle) are distinguished according to the locations of three vertices as follows (not used for high-speed 2DTriangle): V0 Upper edge Long edge Upper triangle Upper edge Upper triangle V0 Long edge V1 Lower edge V1 Lower edge Lower triangle Left-hand triangle V2 Lower triangle Right-hand triangle V2 The following parameters are required for drawing triangles (for high-speed 2DTriangle, X and Y coordinates of each vertex are specified). Ys Xs,Zs,Rs,Gs,Bs,Ss,Ts ,Qs XUs Upper edge start Y coordinates dXUdy dXdy dZdy dRdy dGdy dBdy dSdy dTdy dQdy USN dZdx ,dRdx,dGdx,dBdx, dSdx,dTdx,dQdx Lower edge start Y coordinates XLs dXLdy LSN Note: Be careful about the positional relationship between coordinates Xs, XUs, and XLs. For example, in the above diagram, when a right-hand triangle is drawn using the parameter that shows the coordinates positional relationship Xs (upper edge start Y coordinates) > XUs or Xs (lower edge start Y coordinates) > XLs, the appropriate picture may not be drawn. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 85 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Ys Xs XUs XLs Zs Rs Gs Bs Ss Ts Qs dXdy dXUdy dXLdy dZdy dRdy dGdy dBdy dSdy dTdy dQdy USN LSN dZdx dRdx dGdx dBdx dSdx dTdx dQdx Y coordinates start position of long edge in drawing triangle X coordinates start position of long edge corresponding to Ys X coordinates start position of upper edge X coordinates start position of lower edge Z coordinates start position of long edge corresponding to Ys R color value of long edge corresponding to Ys G color value of long edge corresponding to Ys B color value of long edge corresponding to Ys S coordinate of textures of long edge corresponding to Ys T coordinate of textures of long edge corresponding to Ys Q perspective correction value of texture of long edge corresponding to Ys X DDA value of long edge direction X DDA value of upper edge direction X DDA value of lower edge direction Z DDA value of long edge direction R DDA value of long edge direction G DDA value of long edge direction B DDA value of long edge direction S DDA value of long edge direction T DDA value of long edge direction Q DDA value of long edge direction Count of spans of upper triangle Count of spans of lower triangle Z DDA value of horizontal direction R DDA value of horizontal direction G DDA value of horizontal direction B DDA value of horizontal direction S DDA value of horizontal direction T DDA value of horizontal direction Q DDA value of horizontal direction 9.2.4 Anti-aliasing function CORAL performs anti-aliasing to make jaggies less noticeable and smooth on line edges. To use this function at the edges of primitives, redraw the primitive edges with anti-alias lines. ( The edge of line is blended with a frame buffer color at that time. Ideally please draw sequentially from father object.) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 86 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.3 Bit Map Processing 9.3.1 BLT A rectangular shape in pixel units can be transferred. There are following types of transfer: 1. 2. Transfer from host CPU to Drawing frame memory Transfer between Graphics Memories including Drawing frame Concerning 1 and 2 above, 2-term logic operation is performed between source and destination data and its result can be stored. Setting a transparent color enables a drawing of a specific pixel with transmission. If part of the source and destination of the BLT field are physically overlapped in the display frame, the start address (from which vertex the BLT field to be transferred) must be set correctly. 9.3.2 Pattern data format CORAL can handle three bit map data formats: indirect color mode (8 bits/pixel), direct color mode (16 bits/pixel), and binary bit map (1 bit/pixel). The binary bit map is used for character/font patterns, where foreground color is used for bitmap = 1 pixel, and background color (background color can be set to be transparent by setting) is applied for bitmap = 0 pixels. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 87 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.4 Texture Mapping 9.4.1 Texture size CORAL reads texcel corresponding t o the specified texture coordinates (S, T), and draws that data at the correlated pixel position of the polygon. For the S and T coordinates, the selectable texture data size is any value in the range from 4 to 4096 pixels represented as an exponent of 2. 9.4.2 Texture color Drawing of 8-/16-bit direct color is supported for the texture pattern. For drawing 8-bit direct color, only point sampling can be specified for texture interpolation; only de-curl can be specified for the blend mode. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 88 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.4.3 Texture lapping If a negative or larger than the specified texture pattern size is specified as the texture coordinates (S, T), according to the setting, one of these options (repeat, cramp or border) is selected for the `out-of-range' texture mapping. The mapping image for each case is shown below: Repeat Repeat Cramp Border This just simply masks the upper bits of the applied (S, T) coordinates. When the texture pattern size is 64 x 64 pixels, the lower 6 bits of the integer part of (S, T) coordinates are used for S and T coordinates. Cramp When the applied (S, T) coordinates is either negative or larger than the specified texture pattern size, cramp the (S, T) coordinate as follows instead of texture: S<0 S > Texture X size - 1 S=0 S = Texture X size - 1 Border When the applied (S, T) coordinate is either negative or larger than the specified texture pattern size, the outside of the specified texture pattern is rendered in the `border' color. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 89 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.4.4 Filtering CORAL supports two texture filtering modes: point filtering, and bi-linear filtering. Point filtering This mode uses the texture pixel specified by the (S, T) coordinates as they are for drawing. The nearest pixel in the texture pattern is chosen according to the calculated (S, T) coordinates. 0.5 0.0 1.0 1.5 2.0 0.5 1.0 1.5 2.0 Bi-linear filtering The four nearest pixels specified with (S, T) coordinate are blended according to the distance from specified point and used in drawing. 0.5 0.0 C00 0.5 1.0 1.5 2.0 C01 C11 C10 1.0 1.5 2.0 9.4.5 Perspective correction This function corrects the distortion of the 3D perspective in the texture mapping. For this correction, the `Q' component of the texture coordinates (Q = 1/W) is set based on the W component of 3D coordinates of the vertex. When the texture coordinates are large values, the texture may not be drawn correctly when perspective correction is performed. This phenomenon occurs due to the precision limitation of the arithmetical unit for perspective correction. The coordinates for the texture that cannot be drawn normally vary with the value of the Q component; as a guide, when this value, texture coordinates (S, T) is smaller than -2048 or larger than 2048, normal drawing results are less likely to be obtained. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 90 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.4.6 Texture blending CORAL supports the following three blend modes for texture mapping: De-curl This mode displays the selected texture pixel color regardless of the polygon color. Modulate This mode multiplies the native polygon color (CP ) and selected texture pixel color (C T) and the result is used for drawing. Rendering color is calculated as follows (CO): C0 = CT x CP Stencil This mode selects the display color from the texture color with MSB as a flag. MSB = 1: Texture color MSB = 0: Polygon color 9.4.7 Bi-linear high-speed mode Bi-linear filtering is performed at high speed by creating normal texture data in advance with four-pixel redundancy for one pixel. One pixel requires information of about four pixels, so an area of four times the normal area is used. This data format can only be used only for the bi-linear filtering mode; it cannot be used for the point sampling mode. The color mode is limited to 16-bit color. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 91 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 0 0 1 2 3 4 5 6 7 00 08 16 24 32 40 48 56 1 01 09 17 25 33 41 49 57 2 02 10 18 26 34 42 50 58 3 03 11 19 27 35 43 51 59 4 04 12 20 28 36 44 52 60 5 05 13 21 29 37 45 53 61 6 06 14 22 30 38 46 54 62 7 07 15 23 31 39 47 55 63 Normal texture layout (8 x 8 pixels) 0 0 1 2 3 4 5 6 7 00 08 16 24 32 40 48 56 01 09 17 25 33 41 49 57 08 16 24 32 40 48 56 00 09 17 25 33 41 49 57 01 1 01 09 17 25 33 41 49 57 02 10 18 26 34 42 50 58 09 17 25 33 41 49 57 01 10 18 26 34 42 50 58 02 to to to to to to to to 6 06 14 22 30 38 46 54 62 07 15 23 31 39 47 55 63 14 12 30 38 46 54 62 06 15 13 31 39 47 55 63 07 7 07 15 23 31 39 47 55 63 00 08 16 24 32 40 48 56 15 23 31 39 47 55 63 07 08 16 24 32 40 48 56 00 Texture layout in bi-linear mode (8 x 8 pixels) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 92 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.5 Rendering 9.5.1 Tiling Tiling reads the pixel color from the correlated tiling pattern and maps it onto the polygon. The tiling determines the pixel on the pattern read by pixel coordinates to be drawn, irrespective of position and size of primitive. The tiling pattern size is limited to within 64 x 64 pixels. (at 16-bit color) Example of Tiling 9.5.2 Alpha blending Alpha blending blends the drawn in frame buffer to-be-drawn pixel or pixel already according to the alpha value set in the alpha register. This function cannot be used simultaneously with logic operation drawing. It can be used only when the direct color mode (16 bits/pixel) is used. The blended color C is calculated as shown below when the color of the pixel to be drawn is CP, the color of frame buffer is CF , and the alpha value is A: C = CP x A + (1-A) x CF The alpha value is specified as 8-bit data. 00h means alpha value 0% and FFh means alpha value 100%. When the texture mapping function is enabled, the following blending modes can be selected: Normal Blends post texture mapping color with frame buffer color Stencil Uses MSB of texcel color for ON/OFF control: MSB = 1: Texcel color MSB = 0: Frame buffer color Stencil alpha Uses MSB of texcel color for /OFF control: MSB = 1: Alpha blend texcel color and current frame buffer color MSB = 0: Frame buffer color Note: MSB of frame buffer is drawn MSB of texcel in both stencil and stencil alpha mode. Therefore in case MSB of texcel is MSB=0, a color of frame buffer is frame buffer, but MSB of frame buffer is set to 0. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 93 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.5.3 Logic operation This mode executes a logic operation between the pixel to be drawn and the one already drawn in frame buffer and its result is drawn. Alpha blending cannot be used when this function is specified. Type CLEAR COPY NOP SET COPY INVERTED INVERT AND REVERSE OR REVERSE ID 0000 0011 0101 1111 1100 1010 0010 1011 Operation 0 S D 1 !S !D S & !D S | !D Type AND OR NAND NOR XOR EQUIV AND INVERTED OR INVERTED ID 0001 0111 1110 1000 0110 1001 0100 1101 Operation S&D S|D ! (S & D) ! (S | D) S xor D ! (S xor D) !S & D !S | D 9.5.4 Hidden plane management CORAL supports the Z buffer for hidden plane management. This function compares the Z value of a new pixel to be drawn and the existing Z value in the Z buffer. Display/not display is switched according to the Z -compare mode setting. Define the Z -buffer access options in the ZWRITEMASK mode. The Z compare operation type is determined by the Z compare mode. Either 16 or 8 bits can be selected for the Z-value. 1 0 Code 000 001 010 011 100 101 110 111 Compare Z values, no Z value write overwrite Compare Z values, Z value write Condition Never draw Always draw Draw if pixel Z value < current Z buffer value Draw if pixel Z value current Z buffer value Draw if pixel Z value = current Z buffer value Draw if pixel Z value current Z buffer value Draw if pixel Z value > current Z buffer value Draw if pixel Z value ! = current Z buffer value ZWRITEMASK Z Compare mode NEVER ALWAYS LESS LEQUAL EQUAL GEQUAL GREATER NOTEQUAL MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 94 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.6 Drawing Attributes 9.6.1 Line drawing attributes In drawing lines, the following attributes apply: Line Drawing Attributes Drawing Attribute Line width Broken line Anti-alias Description Line width selectable in range of 1 to 32 pixels Specify broken line pattern in 32-bit data Line edge smoothed when anti -aliasing enabled 9.6.2 Triangle drawing attributes In drawing triangles, the following attributes apply (these attributes are disabled in high-speed 2DTriangle). Texture mapping and tiling have separated texture attributes: Triangle Drawing Attributes Drawing Attribute Shading Alpha blending Alpha blending coefficient Description Gouraud shading or flat shading selectable. In case of indirect color mode, gray scale gouraud shading is possible. Set alpha blending enable/disable per polygon Set color blending ratio of alpha blending How to set gray scale gouraud shading 1. Set Frustum bit of GMDR0 register to 0. 2. Set identity matrix. 3. Set MDR2 register to the below. SM bit = 1, ZC bit = 0, ZW bit = 0, BM bit = 00, TT bit = 00 4. Set GG bit of MDR7 register to 1. 5. Execute drawing by same method as a direct color gouraud shading object. Note: - Please don't use G_BeginE command. - Please don't use floating data format in G_Vertex command. - R (red) parameter is used as a color parameter. 6. Set GG bit of MDR7 register to 0 after rendering. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 95 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.6.3 Texture attributes In texture mapping, the following attributes apply: Texture Attributes Drawing Attribute Texture mode Texture memory mode Texture filter Texture coordinates correction Texture wrap Texture blend mode Bi-linear high-speed mode Description Select either texture mapping or tiling Select either internal texture buffer or external Graphics Memory to use in texture mapping Select either point sampling or bi-linear filtering Select either linear or perspective correction Select either repeat or cramp of texture pattern Select either decal or modulate Texture data is created in a dedicated format to perform high-speed bi-linear filtering. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 96 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.6.4 BLT attributes In BLT drawing, the following attributes apply: BLT Attributes Drawing Attribute Logic operation mode Transparency mode Alpha map mode Description Specify two source logic operation mode Set transparent copy mode and transparent color Blend a color according to alpha map 9.6.5 Character pattern drawing attributes Character Pattern Drawing Drawing Attribute Character pattern enlarge/shrink Character pattern color Transparency/non-transparency Description 2 x 2, x 2 horizontal, 1/2 x 1/2, x 1/2 horizontal Set character color and background color Set background color to transparency/non-transparency MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 97 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.7 Bold Line 9.7.1 Starting and ending points * In the CREMSON bold line mode, the starting and ending points are vertical to the principal axis. * In the CORAL bold line mode, the starting and ending points are vertical to the theoretical line. * Caution: CORAL bold line is generated by different algorithm. Thus drawing position is little bit different from other primitive. CREMSON bold line mode CORAL bold line mode MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 98 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.7.2 Broken line pattern * The broken line pattern vertical to the theoretical line (the CORAL broken line pattern) is supported. * In the CREMSON bold line mode, lines can be drawn using the broken line pattern vertical to the CREMSON-compatible principal axis (the CREMSON broken line pattern), and can also be drawn using the CORAL broken line pattern. * In the CORAL bold line mode, only the CORAL broken line pattern is supported. Broken line pattern made vertical (1) (2) Starting point made vertical; ending point made vertical CORAL bold and broken lines Interpolation of broken line pattern Two types of interpolation modes are supported: * No interpolation mode: Interpolation is not performed. * Broken line pattern reference address fix mode: The same broken line pattern is referenced for several pixels before and after the joint of the bold line. Any pixel count can be set by the user. (1) (2) (1) (2) * * * Edging not performed Interpolation of bold line joint not performed Interpolation of broken line pattern reference performed * * * Edging not performed Interpolation of bold line joint not performed Broken line pattern reference address fixed MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 99 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.7.3 Edging * The edging line is supported. * The line body and edging section can have depth information (Z offset). This mechanics makes it possible to easily represent a good connection of the overlaid part of the edging line. For example, when the line body depth information and edging section depth information are the same, the drawing result of the edging line is like the intersection shown in the figure below. Also, when the line body depth information and edging section depth information are different, the drawing result of the edging line is like the solid intersection shown in the figure below. Intersection Control by depth information Solid intersection Edging MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 100 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.7.4 Interpolation of bold line joint * In the bold line joint interpolation mode, the bold line joint is interpolated using a triangle as shown in the figure below. * The edging line joint is also interpolated using a triangle, but the said depth information makes it possible to represent a good connection as shown in the figure below. * Caution: Sometime joint shape looks not perfect. ( using approximate calculation) Edging interpolation can also be performed. Interpolation using triangle Interpolation of bold line joint MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 101 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 9.8 S h a d o w i n g 9.8.1 Shadowing The Coral supports a shadow primitive which is same shape as a body. A shadow is drawn in a position shifted for a device coordinate(X, Y) by setting the OverlapXY command. And by setting the OverlapZ, it is possible to control a drawing result to avoid twice rendering in alpha blend or logical calculation. - Line Two shadow lines are drawn in a line shadowing. One is a shadow line and another is a shadow composition line. A shadow composition line is used for avoiding an overlap with body line. And drawing priority can be set for rendering performance or anti-aliasing. - Triangle and polygon A shadow primitive are drawn in a triangle and polygon shadowing. Drawing priority is fixed as a body primitive is first. Body line Shadow line Shadow composition line Body primitive Shadow primitive MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 102 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 10 DISPLAY LIST Overview 10.1 Display list is a set of display list commands, parameters and pattern data. All display list commands stored in a display list are executed consequently. The display list is transferred to the display list FIFO by one of the following methods: * Write to display FIFO by CPU * Transfer from main memory to display FIFO by external DMA * Transfer from graphics memory to display FIFO by register setting Display list Command-1 Data 1-1 Data 1-2 Data 1-3 Display list Command-2 Data 2-1 Data 2-2 Data 2-3 Display List MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 103 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 10.1.1 Header format The format of the display list header is shown below. Format List Format Format 1 Format 2 Format 3 Format 4 Format 5 Format 6 Format 7 Format 8 Format 9 Format 10 Format 11 31 24 23 16 15 0 Type Type Type Type Type Type Type Type Type Type Type Reserved Count Reserved Reserved Command Command Command Command Reserved Reserved Reserved Count Reserved Address Reserved Reserved Reserved Count Reserved Reserved Reserved Count Reserved Vertex Flag Vertex Vertex Flag Vertex Flag Description of Each Field Type Command Count Address Vertex Flag Display list type Command Count of data excluding header Address value used at data transfer Vertex number Attribute flag peculiar to display list command Vertex Number Specified in Vertex Code Vertex 00 01 10 11 Vertex number (Line) V0 V1 Setting prohibited Setting prohibited Vertex number (Triangle) V0 V1 V2 Setting prohibited 10.1.2 Parameter format The parameter format of the geometry command depends on the value set in the D field of GMDR0. When the D field is "00", all parameters are handled in the floating-point format. When the D field is "01", colors are handled as the packed RGB format, and others are handled as the fixed-point format. When the D field is "11", XY is handled as the packed integer format, colors are handled as the packed RGB format, and others are handled as the fixed-point format. In the following text, the floating-point format is suffixed by .float, the fixed point format is suffixed by .fixed, and the integer format is suffixed by .int. Set GMDR0 properly to match parameter suffixes. Rendering command parameters conform to the MB86290A data format. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 104 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 10.2 Geometry Commands 10.2.1 Geometry command list CORAL geometry commands and each command code are shown in the table below. Type G_Nop G_Begin G_BeginCont G_BeginE Command See Geometry command code table. Description No operation Specifies primitive type and pre-processes Specifies primitive type (vertex processing in same mode as previous mode) Specifies primitive type and pre-processes This command i s used at execution of the CORAL extended function. Specifies primitive type (vertex processing in same mode as previous mode) This command is used at execution of the CORAL extended function. Ends primitive This command is used at execution of G_Begin or G_BeginCont Ends primitive This command is used at execution of G_BeginE or G_BeginECont. See Geometry command code table. G_BeginECont G_End G_EndE G_Vertex G_VertexLOG G_VertexNopLOG G_Init G_Viewport G_DepthRange G_LoadMatirix G_ViewVolumeXYClip G_ViewVolumeZClip G_ViewVolumeWClip OverlapXYOfft OverlapZOfft See Command table. See Command table. Sets vertex parameter and draws Sets vertex parameter and draws Outputs device coordinates Only outputs device coordinates Initialize geometry engine Scale to screen coordinates (X, Y) and set origin offset Scale to screen coordinates (Z) and set origin offset Load geometric transformation matrix Set boundary value (X, Y) of view volume clip Set boundary value (Z) of view volume clip Set boundary value (W) of view volume clip Sets XY offset at shading Sets Z offset of shade primitive; sets Z offset of edge primitive; sets Z offset of interpolation primitive at 2D drawing with top-left non-applicable Sets starting address of device coordinates output Sets drawing extended mode register Sets geometry extended mode register Sets body color, shade color, and edge color Pass through high-speed 2DLine drawing register Pass through high-speed 2DLine drawing register DC_LogOutAddr SetModeRegister SetGModeRegister SetColorRegister SetLVertex2i SetLVertex2iP See Command table. See Command table. See Command table. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 105 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Type code table Type G_Nop G_Begin G_BeginCont G_End G_Vertex G_VertexLOG G_VertexNopLOG G_Init G_Viewport G_DepthRange G_LoadMatirix G_ViewVolumeXYClip G_ViewVolumeZClip G_ViewVolumeWClip SetLVertex2i SetLVertex2iP SetModeRegister SetGModeRegister OverlapXY0fft OverlapZ0fft DC_LogOutAddr SetColorRegister G_BeginE G_BeginContE G_EndE Code 0010_0000 0010_0001 0010_0010 0010_0011 0011_0000 0011_0010 0011_0011 0100_0000 0100_0001 0100_0010 0100_0011 0100_0100 0100_0101 0100_0110 0111_0010 0111_0011 1100_0000 1100_0001 1100_1000 1100_1001 1100_1100 1100_1110 1110_0001 1110_0010 1110_0011 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 106 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Geometry command code table (1) Integer setup type In setup processing, "XY" is calculated in the integer format and other parameters are calculated in the floating-point format. Command Points.int Lines.int Polygon.int Triangles.int Line_Strip.int Triangle_Strip.int Triangle_Fan.int Code 0001_0000 0001_0001 0001_0010 0001_0011 0001_0101 0001_0111 0001_1000 (2) "Unclipped" integer setup type This command does not clip the view volume. Only "XY" is enabled as the input parameter. In setup processing, "XY" is calculated in the integer format. The screen projection (GMDR0[0]=1) performed using this command is not assured. Command nclip_Points.int nclip_Lines.int nclip_Polygon.int nclip_Triangles.int nclip_Line_Strip.int nclip_Triangle_Strip.int nclip_Triangle_Fan.int Code 0011_0000 0011_0001 0011_0010 0011_0011 0011_0101 0011_0111 0011_1000 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 107 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 10.2.2 Explanation of geometry commands G_Nop (Format 1) 31 24 23 16 15 0 G_Nop Reserved Reserved No operation G_Init (Format 1) 31 24 23 16 15 0 G_Init Reserved Reserved The G_ Init command initializes geometry engine. Execute this command before processing. G_End (Format 1) 31 24 23 16 15 0 G_End Reserved Reserved The G_End command ends one primitive. The G_Vertex command must be specified between the G_Begin or G_BeginCont command and G_End command. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 108 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL G_Begin (Format 5) 31 24 23 16 15 0 G_Begin Command Reserved The G_Begin command sets types of primitive for geometry processing and drawing. A vertex is set and drawn by the G_Vertex command. The G_Vertex command must be specified between the G_Begin or G_BeginCont command and G_End command. Command: Points* Lines* Polygon* Triangles* Line_Strip* Triangle_Strip* Triangle_Fan* Handles primitive as point Handles primitive as independent line Handles primitive as polygon Handles primitive as independent triangle Handles primitive as line strip Handles primitive as triangle strip Handles primitive as triangle fan Usable combinations of GMDR0 mode setting and primitives are as follows: Unclipped primitives (nclip*) (ST,Z,C) (0,0,0) Other than above Point Line Triangle Polygon x x x x Primitives other than unclipped primitives (ST,Z,C) (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,x,x) Point Line Triangle Polygon x (*1) x x x x x x x x x x *1: Please use a geometry lines which coordinates set to same value. And set GMDR1/GMDR1E to "End point drawn" and set MDR1 to "Z compare enable", "solid", "1 pixel line width". G_BeginCont (Format 1) 31 24 23 16 15 0 G_BeginCont Reserved Reserved When the primitive type set by the G_Begin command the last time and drawing mode are not changed, the G_BeginCont command is used instead of the G_Begin command. The G_BeginCont command is processed faster than the G_Begin command. The packet that can be set between the G_End packet set just before and the G_BeginCont packet is only `foreground color setting by the SetRegister packet.' The G_Vertex command must be specified between the G_Begin or G_BeginCont command and G_End command. No primitive type need be specified in the G_BeginCont command. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 109 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL G_BeginE (Format 5) 31 24 23 16 15 0 G_Begin Command Reserved This is the extended G_Begin command. When using the following functions, this command must be executed instead of G_Begin. * Mode register MDR1S/MDR1B/MDR1TL/MDR2S/MDR2TL/GMDR1E/GMDR2E * Polygon with Z or texture mapping * Log output of device coordinates G_VertexLOG/G_VertexNopLOG The G_BeginE command sets types of primitive for geometry processing and drawing. Vertex setting/drawing using the above extended function is performed using the G_Vertex* command. The G_Vertex* command must be set between the G_BeginE command (or the G_BeginECont command) and the G_EndE command. Command: Points* Lines* Polygon* Triangles* Line_Strip* Triangle_Strip* Triangle_Fan* Handles primitive as point Handles primitive as independent line Interpolation of the joint and broken line pattern is not supported. Handles primitive as polygon Handles primitive as independent triangle Handles primitive as line strip Handles primitive as triangle strip Handles primitive as triangle fan Usable combinations of GMDR0 mode setting and primitives are as follows: Unclipped primitives (nclip*) (ST,Z,C) (0,0,0) Other than above Point Line Triangle Polygon x x x x Primitives other than unclipped primitives (ST,Z,C) (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,x,x) Point Line Triangle Polygon(*2) x (*3) x x x x x x x x (*1) *1: Shading is not assured. *2: In case of drawing polygon with Z,ST=1, the algorithm is approximate calculation. The triangle algorithm is more accurate. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 110 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL *3: Please use a geometry lines which coordinates set to same value. And set GMDR1/GMDR1E to "End point drawn" and set MDR1 to "Z compare enable", "solid", "1 pixel line width". MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 111 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL G_BeginECont (Format 1) 31 24 23 16 15 0 G_BeginCont Reserved Reserved When the primitive type set by the G_BeginE command the last time and drawing mode are not changed, the G_BeginECont command is used instead of the G_BeginE command. The G_BeginECont command is processed faster than the G_BeginE command. The packet that can be set between the G_End packet set just before and the G_BeginCont packet is only `foreground color setting by the SetRegister packet.' The G_Vertex command must be specified between the G_Begin or G_BeginCont command and G_End command. No primitive type need be specified in the G_BeginCont command. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 112 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL G_Vertex/G_VertexLOG/G_VertexNopLOG (Format 1) When data format is floating-point format 31 24 23 16 15 0 G_Vertex Reserved X.float Y.float Z.float R.float G.float B.float S.float T.float Reserved When data format is fixed-point format 31 24 23 16 15 0 G_Vertex Reserved X.fixed Y.fixed Z.fixed R.int S.fixed T.fixed G.int Reserved B.int When data format is packed integer format 31 24 23 16 15 0 G_Vertex Y.int Reserved Z.fixed R.ing S.fixed T.fixed G.int Reserved X.int B.int The G_Vertex command sets vertex parameters and processes and draws the geometry of the primitive specified by the G_Begin* command. Note the following when using this command: * Required parameters depend on the setting of the GMDR0 register. Proper values must be set as the mode values of the MDR0 to MDR4 registers to be finally reflected at drawing. That is, when "Z" comparison is made (ZC bit of MDR1 or MDR2 = 1), the Z bit of the GMDR0 register must be set to 1. When Gouraud shading is performed (SM bit of MDR2 = 1), the C bit of the GMDR0 register must be set to 1. When texture mapping is performed (TT bits of MDR2 = 10), the ST bit of the GMDR0 register must be set to 1. * When the Z bit of the GMDR0 register is 0, input "Z" (Zoc) is treated as "0". * Use values normalized to 0 and 1 as texture coordinates (S, T). * When the color RGB is floating-point format, use values normalized to 0 and 1 as the 8-bit color value. For the packed RGB, use the 8-bit color value directly. * The GMDR1 register is valid only for line drawing; it is ignored in primitives other than line. * The GMDR2 register matters only when a triangle (excluding a polygon) is drawn. At primitives other than triangle, set "0". * The use of both G_BeginE(G_BeginEcont) to G_EndE, and G_VertexLOG/NopLOG is not assured. * G_VertexNopLOG, except for the primitive as point is not assured. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 113 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL * A vertex data is processed at every time. For example, the Coral draws interpolation of bold line joint, edging line, shadows at every vertices. G_Viewport (Format 1) 31 24 23 16 15 0 G_Viewport Reserved X_Scaling.float/fixed X_Offset.float/fixed Y_Scaling.float/fixed Y_Offset.float/fixed Reserved The G_Viewport command sets the "X,Y" scale/offset value used when normalized device coordinates (NDC) is transformed into device coordinates (DC). G_DepthRange (Format 1) 31 24 23 16 15 0 G_DepthRange Reserved Z_Scaling.float/fixed Z_Offset.float/fixed Reserved The G_DepthRange command sets the "Z" scale/offset value used when an NDC is transformed into a DC. G_LoadMatrix (Format 1) 31 24 23 16 15 0 G_LoadMatrix Reserved Matrix_a0.float/fixed Matrix_a1.float/fixed Matrix_a2.float/fixed Matrix_a3.float/fixed Matrix_b0.float/fixed Matrix_b1.float/fixed Matrix_b2.float/fixed Matrix_b3.float/fixed Matrix_c0.float/fixed Matrix_c1.float/fixed Matrix_c2.float/fixed Matrix_c3.float/fixed Matrix_d0.float/fixed Matrix_d1.float/fixed Matrix_d2.float/fixed Matrix_d3.float/fixed Reserved The G_LoadMatrix command sets the transformation matrix used when object coordinates (OC) is transformed into clip coordinates (CC). MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 114 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL G_ViewVolumeXYClip (Format 1) 31 24 23 16 15 0 G_ViewVolumeXYClip Reserved XMIN.float/fixed XMAX.float/fixed YMIN.float/fixed YMAX.float/fixed Reserved The G_ViewVolumeXYClip command sets the X,Y coordinates of the clip boundary value in view volume clipping. G_ViewVolumeZClip (Format 1) 31 24 23 16 15 0 G_ViewVolumeZClip Reserved ZMIN.float/fixed ZMAX.float/fixed Reserved The G_ViewVolumeZClip command sets the Z coordinates of the clip boundary value in view volume clipping. G_ViewVolumeWClip (Format 1) 31 24 23 16 15 0 G_ViewVolumeWClip Reserved WMIN.float/fixed Reserved The G_ViewVolumeWClip command sets the W coordinates of the clip boundary value in view volume clipping (minimum value only). MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 115 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL OverlapXYOfft (Format5) 31 OverlapXYOfft Y Offset 24 23 Command 16 15 Reserved X Offset 0 The OverlapXYOfft command sets the XY offset of the shade primitive relative to the body primitive at shading drawing. Shadow shape is same as body. Command: Command ShadowXY ShadowXYcompsition Code 0000_0000 0000_0001 Explanation ShadowXY command sets the XY offset of the shade primitive relative to the body primitive. ShadowXYcomposition command sets the XY offset of the shade synthetic primitive relative to the body primitive. It command synthesizes a shade from the relationship between the XY offset set using ShadowXY and this XY offset. This command is enabled for only lines. OverlapZOfft (Format5) 31 OverlapZOfft don't care Note: When MDR0 ZP = 1, only lower 8 bits are enabled. 31 OverlapZOfft S_Z Offset 24 23 Packed_ONBS B_Z Offset 16 15 Reserved N_Z Offset O_Z Offset 0 24 23 Command 16 15 Reserved Z Offset 0 The OverlapZOfft command sets the Z offset of the shade primitive relative to the body primitive, sets the Z-offset of the edge primitive relative to the body primitive, and sets the Z offset of the interpolation primitive relative to the body primitive, with the top-left rule non-applicable in effect. At this time, the following relationship must be satisfied when, for example, GREATER is specified for the Z value comparison mode: Body primitive > Top-left rule non-applicable interpolation primitive > Edge primitive > Shade primitive Command: Command Origin Code 0000_0000 Explanation Origin command sets the Z offset of the body primitive. When drawing one primitive below the other primitive (for example, when drawing a solid intersection), this Z offset is changed. When drawing an ordinary intersection, set the same Z offset as other primitives. NonTopLeft command sets the Z offset of the interpolation primitive, with the top-left non-applicable. Border command sets the Z o ffset of the edge primitive. Shadow command sets the Z offset of the shade primitive. Packed_ONBS command sets the above four types of Z offsets. NonTopLeft Border Shadow Packed_ONBS 0000_0001 0000_0010 0000_0011 0000_0111 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 116 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DC_LogOutAddr (Format5) 31 OverlapXYOfft 000000 24 23 Command LogOutAddr 16 15 Reserved 0 The DC_LogOutAddr command sets the starting address of the log output destination of the device coordinates. SetModeRegister (Format5) 31 SetModeRegister 24 23 Command MDR1*/MDR2* 16 15 Reserved 0 The SetModeRegister command sets the mode register for shade primitive, for edge primitive, and for top-left non-applicable primitive. At drawing of these primitives, also set the mode register (MDR1/MDR2) for the body primitive, using this packet. Command: Command MDR1 MDR1S MDR1B MDR2 MDR2S MDR2LT Code 0000_0000 0000_0010 0000_0100 0000_0001 0000_0011 0000_0111 Explanation MDR1 command sets MDR1 for the body primitive. MDR1S command sets MDR1 for the shade primitive. MDR1B command sets MDR1 for the edge primitive. MDR2 command sets MDR2 for the body primitive. MDR2S command sets MDR2 for the shade primitive. MDR2LT command sets MDR2 for the top-left non-applicable primitive. SetGModeRegister (Format5) 31 SetGModeRegister 24 23 16 15 Command GMDR1E/GMDR2E 0 Reserved The SetGModeRegister command sets the geometry extended mode register. Command: Command GMDR1E GMDR2E Code 0001_0000 0010_0000 Explanation GMDR1E command sets GMDR1E and at the same time, updates GMDR1. GMDR2E command sets GMDR2E and at the same time, updates GMDR2. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 117 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL SetColorRegister (Format5) 31 SetColorRegister 24 23 Command FGC8/16/24 16 15 Reserved 0 The SetColorRegister command sets the foreground color and background color of the body primitive, shade primitive, and edge primitive. Commands: Command ForeColor BackColor ForeColorShadow BackColorShadow ForeColorBorder BackColorBorder Code 0000_0000 0000_0001 0000_0010 0000_0011 0000_0100 0000_0101 Explanation ForeColor command sets the foreground color for the body primitive. BackColor command sets the background color for the body primitive. ForeColorShadow command sets the foreground color for the shade primitive. BackColorShadow command sets the background color for the shade primitive. ForeColorBorder command sets the foreground color for the edge primitive. BackColorBorder command sets the background color for the edge primitive. SetRegister (Format 2) 31 SetRegister 24 23 Count (Val 0) (Val 1) ... (Val n) 16 15 Address 0 The SetRegister command is upper compatible with CREMSON SetRegister. It can specify the address of a register in the geometry engine. SetLVertex2i (Format 1) 31 SetLVertex2i 24 23 Reserved LX0dc LY0dc 16 15 Reserved 0 The SetLVertex2i command issues the SetRegister_LXOdc/LYOdc command (MB86290A command to set starting vertex at line drawing) in the geometry FIFO interface. This performs processing faster than when the SetRegister_LXOdc/LYOdc command is input directly to the geometry FIFO. SetLVertex2iP (Format 1) 31 SetLVertex2iP LY0dc 24 23 Reserved 16 15 Reserved LX0dc 0 The SetLVertex2iP command supports packed XY of SetLVertex21. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 118 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 10.3 Rendering Command 10.3.1 Command list The following table lists CORAL rendering commands and their command codes. Type Nop Interrupt Sync SetRegister Normal SetVertex2i PolygonBegin PolygonEnd Flush_FB/Z Pixel PixelZ Xvector DrawLine Yvector AntiXvector AntiYvector DrawLine2i DrawLine2iP ZeroVector OneVector TrapRight TrapLeft TriangleFan FlagTriangleFan BltFill ClearPolyFlag DrawBitmapP DrawBitmapLargeP BltCopyP BltCopyAlternateP LoadTextureP BltDraw Bitmap BltDraw TopLeft TopRight BottomLeft BottomRight LoadTexture LoadTILE LoadTexture LoadTILE Command Description No operation Interrupt request to host CPU Synchronization with events Sets data to register Sets data to high-speed 2DTriangle vertex register Initializes border rectangle calculation of multiple vertices random shape Clears polygon flag after drawing polygon Flushes drawing pipelines Draws point Draws point with Z Draws line (principal axis X) Draws line (principal axis Y) Draws line with anti-alias option (principal axis X) Draws line with anti-alias option (principal axis Y) Draws high-speed 2DLine (with vertex 0 as starting point) Draws high-speed 2DLine (with vertex 1 as starting point) Draws right triangle Draws left triangle Draws high-speed 2DTriangle Draws high-speed 2DTriangle for multiple vertices random shape Draws rectangle with single color Clears polygon flag buffer Draws Blt (16-bit) Draws binary bit map (character) Draws Blt (32-bit) Blt transfer from top left coordinates Blt transfer from top right coordinates Blt transfer from bottom left coordinates Blt transfer from bottom right coordinates Loads texture pattern Loads tile pattern Loads texture pattern from local memory Loads tile pattern from local memory Draw DrawPixel DrawPixelZ DrawTrap DrawVertex2i DrawVertex2iP DrawRectP BltTextureP MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 119 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL BltCopyAltAlphaBlendP Alpha blending is supported (see the alpha map). BltCopyAlternateP MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 120 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Type Code Table Type DrawPixel DrawPixelZ DrawLine DrawLine2i DrawLine2iP DrawTrap DrawVertex2i DrawVertex2iP DrawRectP DrawBitmapP BitCopyP BitCopyAlternateP LoadTextureP BltTextureP BltCopyAltAlphaBlendP SetVertex2i SetVertex2iP Draw SetRegister Sync Interrupt Nop 0000_0000 0000_0001 0000_0010 0000_0011 0000_0100 0000_0101 0000_0110 0000_0111 0000_1001 0000_1011 0000_1101 0000_1111 0001_0001 0001_0011 0001_1111 0111_0000 0111_0001 1111_0000 1111_0001 1111_1100 1111_1101 1111_1111 Code MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 121 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Command Code Table (1) Command Pixel PixelZ Xvector Yvector XvectorNoEnd YvectorNoEnd XvectorBlpClear YvectorBlpClear XvectorNoEndBlpClear YvectorNoEndBlpClear AntiXvector AntiYvector AntiXvectorNoEnd AntiYvectorNoEnd AntiXvectorBlpClear AntiYvectorBlpClear AntiXvectorNoEndBlpClear AntiYvectorNoEndBlpClear ZeroVector Onevector ZeroVectorNoEnd OnevectorNoEnd ZeroVectorBlpClear OnevectorBlpClear ZeroVectorNoEndBlpClear OnevectorNoEndBlpClear AntiZeroVector AntiOnevector AntiZeroVectorNoEnd AntiOnevectorNoEnd AntiZeroVectorBlpClear AntiOnevectorBlpClear AntiZeroVectorNoEndBlpClear AntiOnevectorNoEndBlpClear 000_00000 000_00001 001_00000 001_00001 001_00010 001_00011 001_00100 001_00101 001_00110 001_00111 001_01000 001_01001 001_01010 001_01011 001_01100 001_01101 001_01110 001_01111 001_10000 001_10001 001_10010 001_10011 001_10100 001_10101 001_10110 001_10111 001_11000 001_11001 001_11010 001_11011 001_11100 001_11101 001_11110 001_11111 Code MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 122 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Command Code Table (2) Command BltFill BltDraw Bitmap TopLeft TopRight BottomLeft BottomRight LoadTexture LoadTILE TrapRight TrapLeft TriangleFan FlagTriangleFan Flush_FB Flush_Z PolygonBegin PolygonEnd ClearPolyFlag Normal 010_00001 010_00010 010_00011 010_00100 010_00101 010_00110 010_00111 010_01000 010_01001 011_00000 011_00001 011_00010 011_00011 110_00001 110_00010 111_00000 111_00001 111_00010 111_11111 Code MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 123 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 10.3.2 Details of rendering commands All parameters belonging to their command are stored in relevant registers. parameter is explained in the section of each command. Nop (Format1) 31 24 23 16 15 0 The definition of each Nop Reserved Reserved No operation Interrupt (Format1) 31 24 23 16 15 0 Interrupt Reserved Reserved The Interrupt command generates interrupt request to host CPU. Sync (Format9) 31 24 23 16 15 4 0 Sleep Reserved Reserved flag The Sync command suspends all subsequent display list processing until event set in flag detected. Flag: Bit number 4 Bit field name Reserved Bit 0 VBLANK VBLANK Synchronization 0 1 No operation Wait for VSYNC detection 3 Reserved 2 Reserved 1 Reserved 0 VBLANK MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 124 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL SetRegister (Format2) 31 24 23 16 15 0 SetRegister Count (Val 0) (Val 1) (Val n) Address The SetRegister command sets data to sequential registers. Count: Address: Data word count (in double-word unit) Register address Set the value of the address for SetRegister given in the register list. When transferring two or more data, set the starting register address. SetVertex2i (Format8) 31 24 23 16 15 43210 SetVertex2i Xdc Ydc Command Reserved flag vertex The SetVertex2i command sets vertices data for high-speed 2DLine or high-speed 2DTriangle to registers. Commands: Normal PolygonBegin Sets vertex data (X, Y). Starts calculation of circumscribed rectangle for random shape to be drawn. Calculate vertices of rectangle including all vertices of random shape defined between PolygonBegin and PolygonEnd. Flag: Not used SetVertex2iP (Format8) 31 24 23 16 15 43210 SetVertex2i Ydc Command Reserved Xdc flag vertex The SetVertex2iP command sets vertices data for high-speed 2DLine or high-speed 2DTriangle to registers. Only the integer (packed format) can be used to specify these vertices. Commands: Normal PolygonBegin Sets vertices data. Starts calculation of circumscribed rectangle of random shape to be drawn. Calculate vertices of rectangle including all vertices of random shape defined between PolygonBegin and PolygonEnd. Flag: Not used MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 125 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Draw (Format5) 31 24 23 16 15 0 Draw Command Reserved The Draw command executes drawing command. execution must be set at their appropriate registers. Commands: PolygonEnd All parameters required for drawing command Draws polygon end. Fills random shape with color according to flags generated by FlagTriangleFan command and information of circumscribed rectangle generated by PolygonBegin command. Flushes drawing data in the drawing pipeline into th e graphics memory. Place this command at the end of the display list. Flushes Z value data in the drawing pipeline into the graphics memory. When using the Z buffer, place this command together with the Flush_FB command at the end of the display list. Flush_FB Flush_Z DrawPixel (Format5) 31 DeawPixel PXs PYs 24 23 Command 16 15 Reserved 0 The DrawPixel command draws pixel. Command: Pixel Draws pixel without Z value. DrawPixelZ (Format5) 31 24 23 16 15 0 DeawPixel PXs PYs PZs Command Reserved The DrawPixelZ command draws pixel with Z value. Command: PixelZ Draws pixel with Z value. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 126 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DrawLine (Format5) 31 24 23 16 15 0 DrawLine Command LPN LXs LXde LYs LYde Reserved The DrawLine command draws line. registers. Commands: Xvector Yvector XvectorNoEnd YvectorNoEnd XvectorBlpClear YvectorBlpClear XvectorNoEndBlpClear YvectorNoEndBlpClear AntiXvector AntiYvector AntiXvectorNoEnd AntiYvectorNoEnd AntiXvectorBlpClear AntiYvectorBlpClear AntiXvectorNoEndBlpClear It starts drawing after setting all parameters at line draw Draws line (principal axis X). Draws line (principal axis Y). Draws line (principal axis X, and without end point drawing). Draws line (principal axis Y, and without end point drawing). Draws line (principal axis X, and prior to drawing, broken line pattern reference position cleared). Draws line (principal axis Y, and prior to drawing, broken line pattern reference position cleared). Draws line (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). Draws line (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line (principal axis X). Draws anti-alias line (principal axis Y). Draws anti-alias line (principal axis X, and without end point drawing). Draws anti-alias line (principal axis Y, and without end point drawing). Draws anti-alias line (principal axis X and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line (principal axis Y and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiYvectorNoEndBlpClear MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 127 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DrawLine2i (Format7) 31 24 23 16 15 0 DrawLine2i LFXs LFYs Command Reserved 0 0 vertex The DrawLine2i command draws high-speed 2DLine. It starts drawing after setting parameters at the high-speed 2DLine drawing registers. Integer data can only be used for coordinates. Commands: ZeroVector OneVector ZeroVectorNoEnd OneVectorNoEnd ZeroVectorBlpClear Draws line from vertex 0 to vertex 1. Draws line from vertex 1 to vertex 0. Draws line from vertex 0 to vertex 1 (without drawing end point). Draws line from vertex 1 to vertex 0 (without drawing end point). Draws line from vertex 0 to vertex 1 (principal axis X, and prior to drawing, broken line pattern reference position cleared). Draws line from vertex 1 to vertex 0 (principal axis Y, and prior to drawing, broken line pattern reference position cleared). Draws line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). Draws line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line from vertex 0 to vertex 1. Draws anti-alias line from vertex 1 to vertex 0. Draws anti-alias line from vertex 0 to vertex 1 (without end point). Draws anti-alias line from vertex 1 to vertex 0 (without end point). Draws anti-alias line from vertex 0 to vertex 1 (principal axis X and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). OneVectorBlpClear ZeroVectorNoEndBlpClear OneVectorNoEndBlpClear AntiZeroVector AntiOneVector AntiZeroVectorNoEnd AntiOneVectorNoEnd AntiZeroVectorBlpClear AntiOneVectorBlpClear AntiZeroVectorNoEndBlpClear AntiOneVectorNoEndBlpClear MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 128 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DrawLine2iP (Format7) 31 24 23 16 15 0 DrawLine2iP LFYs Command Reserved LFXs vertex The DrawLine2iP command draws high-speed 2DLine. It starts drawing after setting parameters at high-speed 2DLine drawing registers. Only packed integer data can be used for coordinates. Commands: ZeroVector OneVector ZeroVectorNoEnd OneVectorNoEnd ZeroVectorBlpClear Draws line from vertex 0 to vertex 1. Draws line from vertex 1 to vertex 0. Draws line from vertex 0 to vertex 1 (without drawing end point). Draws line from vertex 1 to vertex 0 (without drawing end point). Draws line from vertex 0 to vertex 1 (principal axis X, and prior to drawing, broken line pattern reference position cleared). Draws line from vertex 1 to vertex 0 (principal axis Y, and prior to drawing, broken line pattern reference position cleared). Draws line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). Draws line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line from vertex 0 to vertex 1. Draws anti-alias line from vertex 1 to vertex 0. Draws anti-alias line from vertex 0 to vertex 1 (without end point). Draws anti-alias line from vertex 1 to vertex 0 (without end point). Draws anti-alias line from vertex 0 to vertex 1 (principal axis X and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). OneVectorBlpClear ZeroVectorNoEndBlpClear OneVectorNoEndBlpClear AntiZeroVector AntiOneVector AntiZeroVectorNoEnd AntiOneVectorNoEnd AntiZeroVectorBlpClear AntiOneVectorBlpClear AntiZeroVectorNoEndBlpClear AntiOneVectorNoEndBlpClear MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 129 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DrawTrap (Format5) 31 24 23 16 15 0 DrawTrap Ys Command Xs DXdy XUs DXUdy XLs DXLdy USN LSN Reserved 0 0 0 The DrawTrap command draws Triangle. It starts drawing after setting parameters at the Triangle Drawing registers (coordinates). Commands: TrapRight TrapLeft Draws right triangle. Draws left triangle. DrawVertex2i (Format7) 31 24 23 16 15 0 DrawVertex2i Xdc Ydc Command Reserved 0 0 vertex The DrawVertex2i command draws high-speed 2DTriangle It starts triangle drawing after setting parameters at 2DTriangle Drawing registers. Commands: TriangleFan FlagTriangleFan Draws high-speed 2DTriangle. Draws high-speed 2DTriangle for polygon drawing in the flag buffer. DrawVertex2iP (Format7) 31 24 23 16 15 0 DrawVertex2iP Ydc Command Reserved Xdc vertex The DrawVertex2iP command draws high-speed 2DTriangle It starts drawing after setting parameters at 2DTriangle Drawing registers Only the packed integer format can be used for vertex coordinates. Commands: TriangleFan FlagTriangleFan Draw high-speed 2DTriangle. Draws high-speed 2DTriangle for polygon drawing in the flag buffer. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 130 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DrawRectP (Format5) 31 24 23 16 15 0 DrawRectP RYs RsizeY Command Reserved RXs RsizeX The DrawRectP command fills rectangle. The rectangle is filled with the current color after setting parameters at the rectangle registers. Please set XRES(X resolution) to in 8 byte units when using this command. Commands: BltFill ClearPolyFlag Fills rectangle with current color (single). Fills polygon drawing flag buffer area with 0. frame is defined in RsizeX,Y. The size of drawing DrawBitmapP (Format6) 31 24 23 16 15 0 DrawBitmapP RYs RsizeY Command Count RXs RsizeX (Pattern 0) (Pattern 1) (Pattern n) The DrawBitmapP command draws rectangle patterns. Please set XRES(X resolution) to in 8 byte units when using this command. Commands: BltDraw DrawBitmap Draws rectangle of 8 bits/pixel or 16 bits/pixel. Draws binary bitmap character pattern. Bit 0 is drawn in transparent or background color, and bit 1 is drawn in foreground color. DrawBitmapLargeP (Format11) 31 24 23 16 15 0 DrawBitmapLargeP Rys RsizeY Command Count Reserved Rxs RsizeX (Pattern 0) (Pattern 1) (Pattern n) The DrawBitmapP command draws rectangle patterns. The parameter(count field) could be used up to 32-bit(*1) unlike DrawBitmapP. (*1: The data format of counter field is signed long. Thus actually it is possible to use up to 31-bit.) Please set XRES(X resolution) to in 8 byte units when using this command. Commands: BltDraw Draws rectangle of 8 bits/pixel or 16 bits/pixel. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 131 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL BltCopyP (Format5) 31 24 23 16 15 0 BltCopyP SRYs DRYs BRsizeY Command Reserved SRXs DRXs BRsizeX The BltCopyP command copies rectangle pattern within drawing frame. Please set XRES(X resolution) to in 8 byte units when using this command. Commands: TopLeft TopRight BottomLeft BottomRight Starts BitBlt transfer from top left coordinates. Starts BitBlt transfer from top right coordinates. Starts BitBlt transfer from bottom left coordinates. Starts BitBlt transfer from bottom right coordinates. BltCopyAlternateP (Format5) 31 24 23 16 15 0 BltCopyAlternateP Command SADDR SStride Reserved SRYs DADDR DStride DRYs BRsizeY SRXs DRXs BRsizeX The BltCopyAlternateP command copies rectangle between two separate drawing frames. Please set XRES(X resolution) to in 8 byte units when using this command. And please set SStride and DStride to in 8 byte units. Command: TopLeft Starts BitBlt transfer from top left coordinates. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 132 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL BltCopyAltAlphaBlendP (Format5) 31 24 23 16 15 0 BltCopyAlternateP Command SADDR SStride Reserved SRYs BlendStride BlendRYs DRYs BRsizeY SRXs BlendRXs DRXs BRsizeX The BltCopyAltAlphaBlendP command performs alpha blending for the source (specified using SADDR, SStride, SRXs, SRXy) and the alpha map (specified using ABR (alpha base address), BlendStride, BlendRXs, BlendRYs) and then copies the result of the alpha blending to the destination (specified using FBR (frame buffer base address), XRES (X resolution), DRXs, and DRYs). Please set XRES(X resolution) to in 8 byte units when using this command. And please set SStride and BlendStride to in 8 byte units. Command: reserved Set 0000_0000 to maintain future compatibility. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 133 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11 REGISTER Register List 11.1 11.1.1 Host interface register list Base = HostBase Offset 000 DTC DST DST 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTC DRM DRM DSU DNA DAM DBM DW RSW LREQ SRST DRQ LSTA DTS 004 LTS LTS DTS 008 LSTA 010 DRQ 018 IST 020 IST IMASK 024 IMASK SRST 02C CCF CGE COT 038 LSA 040 LCO 044 LCO LREQ 048 RSW 05C 0f0 CID LSA MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 134 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CN VER MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 135 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.1.2 Graphics memory interface register list Base = HostBase Offset FFFC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MMR TRRD TRCD LOWD TRP SAW TRC TRAS RTS ASW TWR ID CL MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 136 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.1.3 Display controller register list Base = DisplayBase Offset 000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DCE (Display Controller Enable) DCS L45E L23E DEN CKS L1E L0E DCM (Display Control Mode) EEQ SF SC ESY ESY SYNC DCS EOD EDE EEQ DEN CKS EOF L5E L4E L3E L2E L1E L0E SC SF 100 004 008 00C 010 014 018 01C DCEE (Display Controller Extend Enable) DCEM(Display Control Extend Mode) SYNC HTP (H Total Pixels) HDB (H Display Boundary) VSW HSW VTR (V Total Rasters) VDP (V Display Period) WY (Window Y) WH (Window Height) L0M (L0 Mode) L0C HDP (H Display Period) HSP (H Sync pulse Position) VSP (V Sync pulse Position) WX (Window X) WW (Window Width) 020 024 028 02C 110 L0S (L0 Width) L0OA (L0 Origin Address) L0DA (L0 Display Address) L0DY (L0 Display Y) L0EM (L0 Extend Mode) L0H (L0 Height) L0DX (L0 Display X) L0WP L0EC L0PB L0WY (L0 Window Y) L0WH (L0 Window Height) L1M (L1 Mode) L1CS 114 118 L1YC L0WX (L0 Window X) L0WW (L0 Window Width) L1IM L1C 030 034 120 L1S (L1 Width) L1DA (L1 Display Address) L1EM (L1 Extend Mode) L1EC L1PB L2M (L2 Mode) L2C 040 044 048 04C 050 054 130 L2FLP L2S (L2 Width) L2OA0 (L2 Origin Address 0) L2H (L2 Height) L2DA0 (L2 Display Address 0) L2OA1 (L2 Origin Address 1) L2DA1 (L2 Display Address 1) L2DY (L2 Display Y) L2EM (L2 Extend Mode) L2EC L2DX (L2 Display X) L2OM L2WP L2PB L2WY (L2 Window Y) L2WH (L2 Window Height) L2WX (L2 Window X) L2WW (L2 Window Width) 134 138 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 137 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Offset 058 05C 060 064 068 06C 140 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L3M (L3 Mode) L3C L3FLP L3S (L3 Width) L3OA0 (L3 Origin Address 0) L3H (L3 Height) L3DA0 (L3 Display Address 0) L3OA1 (L3 Origin Address 1) L3DA1 (L3 Display Address 1) L3DY (L3 Display Y) L3EM (L3 Extend Mode) L3EC L3DX (L3 Display X) L3PB L3WY (L3 Window Y) L3WH (L3 Window Height) L4M (L4 Mode) L3WX (L3 Window X) L3WW (L3 Window Width) 144 148 070 074 078 07C 080 084 150 L4EC L4C L4FLP L4S (L4 Width) L4OA0 (L4 Origin Address 0) L4H (L4 Height) L4DA0 (L4 Display Address 0) L4OA1 (L4 Origin Address 1) L4DA1 (L4 Display Address 1) L4DY (L4 Display Y) L4EM (L4 Extend Mode) L4OM L4WP L5WP L4DX (L4 Display X) 154 158 088 08C 090 094 098 09C 160 L5EC L4WY (L4 Window Y) L4WH (L4 Window Height) L5M (L5 Mode) L5C L5FLP L4WX (L4 Window X) L4WW (L4 Window Width) L5S (L5 Width) L5OA0 (L5 Origin Address 0) L5H (L5 Height) L5DA0 (L5 Display Address 0) L5OA1 (L5 Origin Address 1) L5DA1 (L5 Display Address 1) L5DY (L5 Display Y) L5EM (L5 Extend Mode) L5OM L5X (L5 Display X) 164 168 L5WY (L5 Window Y) L5WH (L5 Window Height) L5WX (L5 Window X) L5WW (L5 Window Width) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 138 L3OM L3WP FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Offset 0A0 0A4 0A8 0AC 0B0 180 184 0B4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPM CUO1 CUO0 CUE1 CUE0 CUTC (Cursor Transparent Control) CUZT CUTC CUOA0 (CUrsor0 Origin Address) CUY0 (Cursor0 Position Y) CUX0 (Cursor0 Position X) CUOA1 (CUrsor1 Origin Address) CUY1 (Cursor1 Position Y) DLS (Display Layer Select) DLS5 DLS4 DLS3 DLS2 DLS1 DLS0 CUX1 (Cursor1 Position X) DBGC (Display Back Ground Color) L0BLD (L0 Blend) L0BE L0BS L0BP L0BI L0BR L1BLD (L1 Blend) L1BE L1BS L1BP L1BI 188 L1BR L2BLD (L2 Blend) L2BE L2BS L2BP L2BI 18C L2BR L3BLD (L3 Blend) L3BE L3BS L3BP L3BI 190 L3BR L4BLD (L4 Blend) L4BE L4BS L4BP L4BI 194 L4BR L5BLD (L5 Blend) L5BE L5BS L5BI 198 L5BR MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 139 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Offset 0BC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L0TC (L0 Transparent Control) L0ZT L0TC (L0 Transparent Color) L3TR (L3 Transparent Control) L2TR (L2 Transparent Control) L2ZT L2TC (L2 Transparent Color) L3ZT 0C0 L3TR (L3 Transparent Color) L0TEC (L0 Extend Transparency Control) L0EZT 1A0 L0ETC (L0 Extend Transparent Color) L1TEC (L1 Transparent Extend Control) L1EZT 1A4 L1ETC (L1 Extend Transparent Color) L2TEC (L2 Transparent Extend Control) L2EZT 1A8 L2ETC (L2 Extend Transparent Color) L3TEC (L3 Transparent Extend Control) L3EZT 1AC L3ETC (L3 Extend Transparent Color) L4ETC (L4 Extend Transparent Control) L4EZT 1B0 L4ETC (L4 Extend Transparent Color) L5ETC (L5 Extend Transparent Control) L5EZT 1B4 L5ETC (L5 Extend Transparent Color) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 140 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Offset 400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L0PAL0 A R L0PAL1 : L0PAL255 L1PAL0 A R L1PAL1 : L1PAL255 L2PAL0 A R L2PAL1 : L2PAL255 L3PAL0 A R L3PAL1 : L3PAL255 G B G B G B G B 404 : 7FC 800 804 : BFC 1000 1004 : 13FC 1400 1404 : 17FC MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 141 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.1.4 Video Capture register list Base = CaptureBase Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VIE 000 VCM (Video Capture Mode) CM VS VI CSC(Capture SCale) VSCF 004 VSCI 008 HSCI VCS(Video Capture Status) HSCF CE CBM(Capture Buffer Mode) OO 010 CBW CBOA(Capture Bauffer Origin Address) 014 CBOA CBLA(Capture Buffer Limit Address) 018 CBLA 01C 020 028 CIVSTR CIVEND CHP(Capture Horizontal Pixel) CHP CVP(Capture Vertical Pixel) 02C CVPP 040 CVLPF 4000 CLPF(Capture Low Pass Filter) CHLPF CDCN(Capture Data Count for NTSC) BDCN CDCP(Capture Data Count for PAL) 4004 BDCP VDCP VDCN CVPN CIHSTR CIHEND MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 142 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.1.5 Drawing engine register list The parenthesized value in the Offset field denotes the absolute address used by the SetRegister command. Base = DrawBase Offset 000 (000) 004 (001) 008 (002) 00C (003) 010 (004) 014 (005) 018 (006) 01C (007) 020 (008) 040 (010) 044 (011) 048 (012) 04C (013) 050 (014) 054 (015) 058 (016) 05C (017) 060 (018) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ys S S S S Int Xs Frac S S S S Int dXdy Frac S S S S Int XUs Frac S S S S Int dXUdy Frac S S S S Int XLs Frac S S S S Int dXLdy Frac S S S S Int USN Frac 0 0 0 0 Int LSN 0 0 0 0 0 Int Rs 0 0 0 0 0 0 0 0 0 Int dRdx Frac S S S S S S S S Int dRdy Frac S S S S S S S S Int Gs Frac 0 0 0 0 0 0 0 0 Int dGdx Frac S S S S S S S S Int dGdy Frac S S S S S S S S Int Bs Frac 0 0 0 0 0 0 0 0 Int dBdx Frac S S S S S S S S Int dBdy Frac S S S S S S S S Int Frac MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 143 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 080 (020) 084 (021) 088 (022) 0C0 (030) 0C4 (031) 0C8 (032) 0CC (033) 0D0 (034) 0D4 (035) 0D8 (036) 0DC (037) 0E0 (038) 140 (050) 144 (051) 148 (052) 14C (053) 150 (054) 154 (055) 158 (056) Zs 0 Int dZdx Frac S Int dZdy Frac S Int Ss Frac S S S Int dSdx Frac S S S Int dSdy Frac S S S Int Ts Frac S S S Int dTdx Frac S S S Int dTdy Frac S S S Int Qs INT Frac 0 0 0 0 0 0 0 Frac dQdx INT S S S S S S S Frac dQdy INT S S S S S S S Frac LPN 0 0 0 0 Int LXs 0 S S S S Int LXde Int Frac S S S S S S S S S S S S S S S Frac LYs S S S S Int LYde Int Frac S S S S S S S S S S S S S S S Frac LZs S Int LZde Frac S Int Frac MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 144 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Offset 180 (060) 184 (061) 188 (062) 200 (080) 204 (081) 208 (082) 20C (083) 240 (090) 244 (091) 248 (092) 24C (093) 250 (094) 254 (095) 258 (096) 25C (097) 260 (098) 264 (099) 280 (09A) 28C (0A3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PXdc 0 0 0 0 0 Int PYdc 0 0 0 0 0 Int PZdc 0 0 Int RXs 0 0 0 0 0 Int RYs 0 0 0 0 0 Int RsizeX 0 0 0 0 0 Int RsizeY 0 0 0 0 0 Int SADDR 0 0 0 0 0 0 0 0 Address SStride 0 0 0 0 Int SRXs 0 0 0 0 0 Int SRYs 0 0 0 0 0 Int DADDR 0 0 0 0 0 0 0 0 Address DStride 0 0 0 0 Int DRXs 0 0 0 0 0 Int DRYs 0 0 0 0 0 Int BRsizeX 0 0 0 0 0 Int BRsizeY 0 0 0 0 0 Int TColor 0 PNBPI 0 Color PN MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 145 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Offse t 3E0 (0F8) 400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BLPO BCR CTR CE FE FD (100) 404 (-) 408 (-) 40C (-) 410 (-) 414 (-) 418 (-) 420 (108) 424 FCNT IFSR NF FE FF SS DS PS IFCNT FCNT SST SS DS DS PST PS EST FD NF CE MDR0 CY CF MDR1/MDR1S/MDR1B CX ZP BSV BSH ZW BP (109) 428 (10a) 42C TT LW LOG BM ZCL MDR2/MDR2S/MDR2TL ZW ZC BL LOG MDR3 BA BM ZCL TF (10b) 430 (10c) 43C (10f) TAB TBL TWS TWT MDR4 LOG MDR7 PGH PTH PZH LTH GG EZ TC BM MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 146 TE SM ZC AS FE FF FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Offset 440 (110) 444 (111) 448 (112) 44C (113) 450 (114) 454 (115) 458 (116) 45C (117) 460 (118) 464 (119) 468 (11a) 46C (11b) 470 (11C) 474 (11D) 480 (120) 484 (121) 488 (122) 48C (123) 494 (125) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FBR FBASE XRES XRES ZBR ZBASE TBR TBASE PFBR PFBASE CXMIN CLIPXMIN CXMAX CLIPXMAX CYMIN CLIPYMIN CYMAX CLIPYMAX TXS TXSN TIS TISN TOA XBO SHO SHOFFS ABR ABASE FC FGC8/16 BC BGC8/16 ALF A BLP TBC BC8/16 TISM TXSM MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 147 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Offset 540 (150) 544 (151) 548 (152) 54C (153) 580 (160) 584 (161) 588 (162) 58C (163) 590 (164) 594 (165) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LX0dc 0 0 0 0 Int LY0dc 0 0 0 0 0 Int LX1dc 0 0 0 0 0 Int LY1dc 0 0 0 0 0 Int X0dc 0 0 0 0 0 Int Y0dc 0 0 0 0 0 Int X1dc 0 0 0 0 0 Int Y1dc 0 0 0 0 0 Int X2dc 0 0 0 0 0 Int Y2dc 0 0 0 0 0 Int 0 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 148 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.1.6 Geometry engine register list The parenthesized value in the Offset field denotes the absolute address used by the SetRegister command. Base = GeometryBase Offset 000 FO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GCTR FCNT GMDR0 CF NF FE FF (-) 040 (2010) 044 (2011) - 048 (2012) - 400 (-) GS SS PS DF ST C Z GMDR1 EP BO AA CF CF AA GMDR1E UW TM BM BP SP PO BO TC BC EP LV GMDR2 FD GMDR2E SP FD TL DFIFOG MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 149 F FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2 Explanation of Register Terms appeared in this chapter are explained below: 1. 2. 3. 4. Register address Indicates address of register Bit number Indicates bit number Bit field name Indicates name of each bit field included in register R/W Indicates access attribute (read/write) of each field Each symbol shown in this section denotes the following: R0 W0 R W RX RW "0" always read at read. Write access is Don't care. Only "0" can be written. Read enabled Write enabled Read enabled (read values undefined) Read and write enabled RW0 Read and write 0 enabled 5. Initial value Indicates initial value of immediately before the reset of each bit field. 6. Handling of reserved bits "0" is recommended for the write value so that compatibility can be maintained with future products. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 150 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.1 Host interface registers DTC (DMA Transfer Count) Register HostBaseAddress + 00H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved DTC R/W R0 RW Initial value 0 Don't care DTC is a readable/writable 32-bit register which sets the transfer count in either one long-word (32 bits) or 32 bytes units. When "1h" is set transfer is performed once. However, when "0h" is set, it indicates the maximum transfer count and 16M (16,777,216) data are transferred. During DMA transfer, the remaining transfer count is shown, therefore, the register value cannot be overwritten until DMA transfer is completed. Note: This register need not be set in a mode in which Dual DMA ACK is not used, or the V832 mode. DSU (DMA Set Up) Register HostBaseAddress + 04H address Bit number 7 6 5 Bit field name Reserved R/W R0 Initial value 0 4 3 2 DAM RW 0 1 DBM RW 0 0 DW RW 0 Bit 0 DW (DMA Word) Specifies DMA transfer count 0: 1: 1-double word (32 bits) per DMA transfer 8-double words (32 bytes) per DMA transfer (only SH4) Bit 1 DBM (DMA Bus request Mode) Selects DREQ mode used in DMA transfer in dual-address mode 0: 1: DREQ is not negated during DMA transfer irrespective of cycle steal or burst mode. DREQ is negated irrespective of cycle steal or burst mode when CORAL cannot receive data (that is, when Ready cannot be returned immediately). When CORAL is ready to receive data, DREQ is reasserted (When DMA transfer is performed in the single-address mode, DREQ is controlled automatically). Bit 2 DAM (DMA Address Mode) Selects DMA address mode in issuing external request 0: 1: Dual address mode Single address mode (SH4 only) Bit 3 DNA (Dual address No Ack mode) This bit is selected when using the dual-address-mode DMA that does not use the ACK signal. 0: 1: Uses dual-address-mode DMA that uses ordinary ACK signal Uses dual-address-mode DMA that does not use ACK signal Detection of the DREQ edge is supported; DREQ is negated per transfer. When data cannot be received irrespective of the Bit1 setting, DREQ continues being negated. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 151 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DRM (DMA Request Mask) Register HostBaseAddress + 05H address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 DRM RW 0 This register enables the DMA request. Setting "1" to this register to temporarily stop the DMA request from the CORAL. The external request is enabled by setting "0" to this register. DST (DMA STatus) Register HostBaseAddress + 06H address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 DST R 0 This register indicates the DMA transfer status. DST is set to "1" during DMA transfer. This state is cleared to "0" when the DMA transfer is completed. DTS (DMA Transfer Stop) Register HostBaseAddress + 08H address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 DTS RW 0 This register suspends DMA transfer. An ongoing DMA transfer is suspended by setting DTS to "1". In the dual-address without ACK mode, to end the DMA transfer, write "1" to this register after CPU DMA transfer. LTS (display Transfer Stop) Register HostBaseAddress + 09H address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 LTS RW 0 This register suspends DisplayList transfer. Ongoing DisplayList transfer is suspended by setting LTS to "1". LSTA (displayList transfer STAtus) Register HostBaseAddress + 10H address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 LSTA R 0 This register indicates the DisplayList transfer status from Graphics Memory. LSTA is set to "1" while DisplayList transfer is in progress. This status is cleared to 0 when DisplayList transfer is completed MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 152 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DRQ (DMA ReQquest) Register HostBaseAddress + 18H address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 DRQ RW1 0 This register starts sending external DMA request. DMA transfer using the external request handshake is triggered by setting DRQ to "1". The external DREQ signal cannot be issued when DMA is masked by the DRM register. This register cannot be written "0". When DMA transfer is completed, this status is cleared to "0". IST (Interrupt STatus) Register HostBaseAddress + 20H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved Resv Reserved IST IST R/W R0 R0W0 R0 RW0 RW0 Initial value 0 0 0 0 0 This register indicates the current interrupt status. It shows that an interrupt request is issued when "1" is set to this register. The interrupt status is cleared by writing "0" to this register. Bit 0 CERR (Command Error Flag) Indicates drawing command execution error interrupt CEND (Command END) Indicates drawing command end interrupt VSYNC (Vertical Sync.) Indicates vertical interrupt synchronization FSYNC (Frame Sync.) Indicates frame synchronization interrupt SYNCERR (Sync. Error) Indicates external synchronization error interrupt Reserved This field is provided for testing. Normally, the read value is "0", but note that it may be "1" when a drawing command error (Bit 0) has occurred. Bit 1 Bit 2 Bit 3 Bit 4 Bit 17 and 16 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 153 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL IMASK (Interrupt MASK) Register HostBaseAddress + 24H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved Resv Reserved IMASK IMASK R/W R0 R0W0 R0 RW RW Initial value 0 0 0 0 0 This register masks interrupt requests. Even when the interrupt request is issued for the bit to which "0" is written, interrupt signal is not asserted for CPU. Bit 0 CERRM (Command Error Interrupt Mask) Masks drawing command execution error interrupt Bit 1 CENDM (Command Interrupt Mask) Masks drawing command end interrupt Bit 2 VSYNCM (Vertical Sync. Interrupt Mask) Masks vertical synchronization interrupt Bit 3 FSYNCH (Frame Sync. Interrupt Mask) Masks frame synchronization interrupt Bit 4 SYNCERRM (Sync Error Mask) Masks external synchronization error interrupt SRST (Software ReSeT) Register HostBaseAddress + 2CH address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 SRST W1 0 This register controls software reset. When "1" is set to this register, a software reset is performed. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 154 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL LSA (displayList Source Address) Register HostBaseAddress + 40H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved LSA R/W R0 RW R0 Initial value 0 Don't care 0 This register sets the DisplayList transfer source address. When DisplayList is transferred from Graphics Memory, set the transfer start address of DisplayList stored in Graphics Memory. Since the lower two bits of this register are always treated a "0", DisplayList must be 4 s -byte aligned. The values set at this register do not change during or after transfer. LCO (displayList Count) Register HostBaseAddress + 44H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved LCO R/W R0 RW Initial value 0 Don't care This register sets the DisplayList transfer count. Set the display list transfer count by the long word. When "1h" is set, 1-word data is transferred. When "0" is set, it is considered to be the maximum count and 16M (16,777,216) words of data are transferred. The values set at this register do not change during or after transfer. LREQ (displayList transfer REQuest) Register HostBaseAddress + 48H address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 LREQ RW1 0 This register triggers DisplayList transfer from the Graphics Memory. Transfer is started by setting LREQ to "1". The DisplayList is transferred from the Graphics Memory to the internal display list FIFO. Access to the display list FIFO by the CPU or DMA is disabled during transfer. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 155 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL RSW (Register location Switch) Register HostBaseAddress + 5CH address Bit number 7 6 5 Bit field name R/W Initial value 4 3 2 1 0 Reserved R0 0 RSW RW 0 In SH3 or SH4 mode, set this register when moving the register area from the center (1FC0000) to the end of the CORAL area (3FC0000). This move can be performed when "1" is written to this register. Set this register at the first access after reset. Access CORAL after about 20 bus clocks after setting the register. CID (Chip ID register) Register HostBaseAddress + f0 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CN VER R/W R0 R R Initial value 0 0000_0011 0 This is the chip identification register. Bit 7 to 0 VER (VERsion) This field indicates the chip's unique version number. Note that the unique version number for the ES version and that of the mass-produced version are different. 0000_0000 0000_0001 0000_0010 others ES Reserved Reserved for LQ Reserved Bit 15 to 8 CN (Chip Name) This field indicates the chip name. 0000_0000 0000_0001 0000_0010 0000_0011 others Reserved Reserved Reserved CORAL Reserved MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 156 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CCF (Change of Clock Frequency) Register HostBaseAddress + 38H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CGE COT Reserved R/W RW0 RW RW RW0 Initial value 0 00 00 0 This register changes the operating frequency. Bit 19 and 18 CGE (Clock select for Geometry Engine) Selects the clock for the geometry engine 11 10 01 00 Reserved 166 MHz 133 MHz 100 MHz Bit 17 and 16 COT (Clock select for the others except-geometry engine) Selects the clock for other than the geometry engine 11 10 01 00 Reserved Reserved 133 MHz 100 MHz Notes: 1. Write "0" to the bit field other than the above ([31:20], [15:00]). 2. Operation is not assured when the clock setting relationship is CGE < COT. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 157 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.2 Graphics memory interface registers MMR (Memory I/F Mode Register) Register HostBaseAddress + FFFC H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name *1 tWR Reserved *1 *1 TRRD TRC TRP TRAS TRCD LOWD RTS RAW ASW CL R/W Initial value RW RW R R1 W0 R RW RW RW RW RW RW RW RW RW RW 0 0 Don't care 1 0 00 0000 00 000 00 00 000 000 0 000 *1: Reserved This register sets the mode of the graphics memory interface. A value must be written to this register after a reset. ( hen default setting is performed, a value must also be written to this register.) Only W write once to this register; do not change the written value during operation. This register is not initialized at a software reset. Bit 2 to 0 CL (CAS Latency) Sets the CAS latency. Write the same value as this field, to the mode register for SDRAM 011 010 Other than the above CL3 CL2 Setting disabled Bit 3 ASW (Attached SDRAM bit Width) Sets the bit width of the data bus (memory bus width mode) 1 0 64 bit 32 bit Bit 6 to 4 SAW (SDRAM Address Width) Sets the bit width of the SDRAM address 001 111 110 101 100 000 Other than the above 15 bit BANK 2 bit ROW 13 bit COL 9 bit SDRAM 14 bit BANK 2 bit ROW 12 bit COL 9 bit SDRAM 14 bit BANK 2 bit ROW 12 bit COL 8 bit SDRAM 13 bit BANK 2 bit ROW 11 bit COL 8 bit SDRAM 12 bit BANK 1 bit ROW 11 bit COL 8 bit FCRAM 14 bit BANK 2 bit ROW 12 bit COL 8 bit SDRAM Setting disabled Bit 9 to 7 RTS (Refresh Timing Setting) Sets the refresh interval 000 111 001 to 110 Refresh is performed every 384 internal clocks. Refresh is performed every 1552 internal clocks. Refresh is performed every `64 x n' internal clocks in the 64 to 384 range. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 158 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Bit 11 and 10 LOWD Sets the count of clocks secured for the period from the instant the ending data is output to the instant the write command is issued. 10 00 Other than the above 2 clocks 2 clocks Setting disabled Bit 13 and 12 TRCD Sets the wait time secured from the bank active to CAS. The clock count is used to express the wait time. 11 10 01 00 3 clocks 2 clocks 1 clock 0 clock Bit 16 to 14 TRAS Sets the minimum time for 1 bank active. The clock count is used to express the minimum time. 111 110 101 100 011 010 Other than the above 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks Setting disabled Bit 18 and 17 TRP Sets the wait time secured from the pre-charge to the bank active. The clock count is used to express the wait time. 11 10 01 3 clocks 2 clocks 1 clock Bit 22 to 19 TRC This field sets the wait time secured from the refresh to the bank active. The clock count is used to express th e wait time. 1010 1001 1000 0111 0110 0101 0100 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 159 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 0011 Other than the above 3 clocks Setting disabled Bit 24 and 23 TRRD Sets the wait time secured from the bank active to the next bank active. The clock count is used to express the wait time. 11 10 3 clocks 2 clocks Bit 26 Reserved Always write "0" at write. "1" is always read at read. Bit 30 TWR Sets the write recovery time (the time from the write command to the read or to the pre-charge command). 1 0 2 clocks 1 clock MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 160 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.3 Display control register DCM (Display Control Mode) / DCEM (Display Control Extend Mode) Register DisplayBaseAddress + 00H (DisplayBaseAddress + 100H) address Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Bit field name CKS Reserved SC EEQ ODE Reserved Reserved SF ESY R/W RW RW0 RW RW RW RX RX RW RW Initial value 0 0 01110 (DCM) 11101 (DCEM) 0 X 0 1 1 0 SYNC RW 00 This register controls the display count mode. It is not initialized by a software reset. This register is mapped to two addresses. The difference between the two registers is the format of the frequency division rate setting (SC). Bit 1 to 0 SYNC (Synchronize) Set synchronization mode X0 10 11 Non-interlace mode Interlace mode Interlace video mode Bit 2 ESY (External Synchronize) Sets external synchronization mode 0: 1: External synchronization disabled External synchronization enabled Bit 3 SF (Synchronize signal format) Sets format of synchronization (VSYNC, HSYNC) signals 0: 1: Negative logic Positive logic Bit 7 EEQ (Enable Equalizing pulse) Sets CCYNC signal mode 0: 1: Does not insert equalizing pulse into CCYNC signal Inserts equalizing pulse into CCYNC signal Bit 13 to 8 SC (Scaling) Divides display reference clock by the preset ratio to generate dot clock Offset = 0 x00000 x00001 x00010 X00011 : x11111 Frequency division rate = 1/64 Frequency not divided Frequency division rate = 1/4 Frequency division rate = 1/6 Frequency division rate = 1/8 Offset = 100H 000000 000001 000010 000011 : 111111 Frequency division rate = 1/64 Frequency not divided Frequency division rate = 1/2 Frequency division rate = 1/3 Frequency division rate = 1/4 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 161 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL When n is set, with Offset = 0, the frequency division rate is 1/(2n + 2). When m is set, with Offset = 100h, the frequency division rate is 1/(m + 1). Basically, these are setting parameters with the same function (2n + 2 = m + 1). Because of this, m = 2 n + 1 is established. When n is set to the SC field with Offset = 0, 2n + 1 is reflected with Offset = 100h. Also, when PLL is selected as the reference clock, frequency division rates 1/1 to 1/5 are non-functional even when set; other frequency division rates are assigned. Bit 15 CKS (Clock Source) Selects reference clock 0: 1: Internal PLL output clock DCLKI input MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 162 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DCE (Display Controller Enable) Register DisplayBaseAddress + 02H address Bit number 15 14 13 12 11 10 9 8 Bit field name DEN Reserved R/W RW R0 Initial value 0 0 7 6 5 4 3 2 1 L45E L23E L1E RW RW RW 0 0 0 0 L0E RW 0 This register controls enabling the video signal output and display of each layer. Layer enabling is specified in four-layer units to maintain backward compatibility with previous products. Bit 0 L0E (L0 layer Enable) Enables display of the L0 layer. The L0 layer corresponds to the C layer for previous products. 0: 1: Does not display L0 layer Displays L0 layer Bit 1 L1E (L1 layer Enable) Enables d isplay of the L1 layer. The L1 layer corresponds to the W layer for previous products. 0: 1: Does not display L1 layer Displays L1 layer Bit 2 L23E (L2 & L3 layer Enable) Enables simultaneous display of the L2 and L3 layers. These layers correspond to the M layer for previous products. 0: 1: Does not display L2 and L3 layer Displays L2 and L3 layer Bit 3 L45E (L4 & L5 layer Enable) Enables simultaneous display of the L4 and L5 layers. These layers correspond to the B layer for previous products. 0: 1: Does not display L4 and L5 layer Displays L4 and L5 layer Bit 15 DEN (Display Enable) Enables display 0: 1: Does not output display signal Outputs display signal MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 163 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DCEE (Display Controller Extend Enable) Register DisplayBaseAddress + 102H address Bit number 15 14 13 12 11 10 9 Bit field name DEN Reserved R/W RW R0 Initial value 0 0 8 7 6 5 L5E RW 0 4 L4E RW 0 3 2 L3E L2E RW RW 0 0 1 L1E RW 0 0 L0E RW 0 This register controls enabling the video signal output and display of each layer. This register has the same function as DCE. Bit 0 L0E (L0 layer Enable) Enables L0 layer display 0: 1: Does not display L0 layer Displays L0 layer Bit 1 L1E (L1 layer Enable) Enables L1 layer display 0: 1: Does not display L1 l ayer Displays L1 layer Bit 2 L2E (L2 layer Enable) Enables L2 layer display 0: 1: Does not display L2 layer Displays L2 layer Bit 3 L3E (L3 layer Enable) Enables L3 layer display 0: 1: Does not display L3 layer Displays L3 layer Bit 4 L4E (L4 layer Enable) Enables L4 layer display 0: 1: Does not display L4 layer Displays L4 layer Bit 5 L5E (L5 layer Enable) Enables L5 layer display 0: 1: Does not display L5 layer Displays L5 layer Bit 15 DEN (Display Enable) Enables display 0: 1: Does not output display signal Outputs display signal MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 164 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL HTP (Horizontal Total Pixels) Register DisplayBaseAddress + 06H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 HTP RW Don't care 6 4 3 2 1 0 This register controls the horizontal total pixel count. Setting value + 1 is the total pixel count. HDP (Horizontal Display Period) Register DisplayBaseAddress + 08H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 HDP RW Don't care 6 4 3 2 1 0 This register controls the total horizontal display period in unit of pixel clocks. Setting value + 1 is the pixel count for the display period. HDB (Horizontal Display Boundary) Register DisplayBaseAddress + 0AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 HDB RW Don't care 6 4 3 2 1 0 This register controls the display period of the left part of the window in unit of pixel clocks. Setting value + 1 is the pixel count for the display period of the left part of the window. When the window is not divided into right and left before display, set the same value as HDP. HSP (Horizontal Synchronize pulse Position) Register DisplayBaseAddress + 0CH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 HSP RW Don't care 6 4 3 2 1 0 This register controls the pulse position of the horizontal synchronization signal in unit of pixel clocks. When the clock count since the start of the display period reaches setting value + 1, the horizontal synchronization signal is asserted. HSW (Horizontal Synchronize pulse Width) Register DisplayBaseAddress + 0EH address Bit number 7 6 5 Bit field name R/W Initial value 4 HSW RW Don't care 3 2 1 0 This register controls the pulse width of the horizontal synchronization signal in unit of pixel clocks. Setting value + 1 is the pulse width clock count. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 165 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL VSW (Vertical Synchronize pulse Width) Register DisplayBaseAddress + 0FH address Bit number 7 6 5 Bit field name Reserved R/W R0 Initial value 0 4 3 VSW RW Don't care 2 1 0 This register controls the pulse width of vertical synchronization signal in unit of raster. Setting value + 1 is the pulse width raster count. VTR (Vertical Total Rasters) Register DisplayBaseAddress + 12H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 VTR RW Don't care 6 4 3 2 1 0 This register controls the vertical total raster count. Setting value + 1 is the total raster count. For the interlace display, Setting value + 1.5 is the total raster count for 1 field; 2 x setting value + 3 is the total raster count for 1 frame (see Section 8.3.2). VSP (Vertical Synchronize pulse Position) Register DisplayBaseAddress + 14H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 VSP RW Don't care 6 4 3 2 1 0 This register controls the pulse position of vertical synchronization signal in unit of raster. The vertical synchronization pulse is asserted starting at the setting value + 1st raster relative to the display start raster. VDP (Vertical Display Period) Register DisplayBaseAddress + 16H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 VDP RW Don't care 6 4 3 2 1 0 This register controls the vertical display period in unit of raster. raster to be displayed. Setting value + 1 is the count of MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 166 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L0M (L0 layer Mode) Register DisplayBaseAddress + 20H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L0C Reserved Reserved LOW Reserved CH R/W RW R0 R0 RW R0 RW Initial value 0 0 0 Don't care 0 Don't care Bit 11 to 0 L0H (L0 layer Height) Specifies the height of the logic frame of the L0 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L0W (L0 layer memory Width) Sets the memory width (stride) of the logic frame of the L0 layer in 64-byte units Bit 31 L0C (L0 layer Color mode) Sets the color mode for L0 layer 0 1 Indirect color (8 bits/pixel) mode Direct color (16 bits/pixel) mode L0EM (L0-layer Extended Mode) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 110H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ----L0EC Reserved L0PB Reserved RW R0 RW R0 0 0 432 1 0 L0WP RW 0 Bit 0 L0 WP (L0 layer Window Position enable) Selects the display position of L0 layer 0 1 Compatibility mode display (C layer supported) Window display Bit 23 to 20 L0PB (L0 layer Palette Base) Shows the value added to the index when subtracting palette of L0 layer. 16 times of setting value is added. Bit 31 and 30 L0EC (L0 layer Extended Color mode) Sets extended color mode for L0 layer 00 01 1x Mode determined by L0C Direct color (24 bits/pixel) mode Reserved MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 167 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L0OA (L0 layer Origin Address) Register DisplayBaseAddress + 24H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0OA R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L0 layer. Since lower 4 bits are fixed at "0", address 16-byte-aligned. L0DA (L0-layer Display Address) Register DisplayBaseAddress + 28H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0DA R/W R0 RW Initial value 0 Don't care This register sets the display origin address of the L0 layer. For the direct color mode (16 bits/pixel), the lower 1 bit is "0", and this address is treated as being aligned in 2 bytes. L0DX (L0-layer Display position X) Register DisplayBaseAddress + 2CH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L0 layer on the basis of the origin of the logic frame in pixels. L0DY (L0-layer Display position Y) Register DisplayBaseAddress + 2EH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L0 layer on the basis of the origin of the logic frame in pixels. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 168 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L0WX (L0 layer Window position X) Register DisplayBaseAddress + 114H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WX RW 4 3 2 1 0 This register sets the X coordinates of the display position of the L0 layer window. L0WY (L0 layer Window position Y) Register DisplayBaseAddress + 116H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WY RW 4 3 2 1 0 This register sets the Y coordinates of the display position of the L0 layer window. L0WW (L0 layer Window Width) Register DisplayBaseAddress + 118H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WW RW Don't care 4 3 2 1 0 This register controls the horizontal direction display size ( idth) of the L0 layer w w indow. specify "0". L0WH (L0 layer Window Height) Register DisplayBaseAddress + 1 1AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 Do not 9 8 7 6 5 L0WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L0 layer window. Setting value + 1 is the height. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 169 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L1M (L1-layer Mode) Register DisplayBaseAddress + 30H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 5 4 3 2 1 0 Bit field name L1C L1YC L1CS L1IM Reserved L1W Reserved R/W RW RW RW RW R0 RW R0 Initial value 0 0 0 0 0 Don't Care 0 Bit 23 to 16 L1W (L1 layer memory Width) Sets the memory width (stride) of the logic frame of the L layer in unit of 64 bytes Bit 28 L1IM (L1 layer Interlace Mode) Sets video capture mode when L1CS in capture mode 0: 1: Normal mode For non-interlace display, displays captured video graphics in WEAVE mode For interlace and video display, buffers are managed in frame units (pair of odd field and even field). Bit 29 L1CS (L1 layer Capture Synchronize) Sets whether the layer is used as normal display layer or as video capture 0: 1: Normal mode Capture mode Bit 30 L1YC (L1 layer YC mode) Sets color format of L1 layer The YC mode must be set for video capture. 0: 1: RGB mode YC mode Bit 31 L1C (L1 layer Color mode) Sets color mode for L1 layer 0: 1: Indirect color (8 bits/pixel) mode Direct color (16 bits/pixel) mode MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 170 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L1EM (L1 layer Extended Mode) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 120H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - L1EC Reserved L1PB Reserved RW R0 RW R0 0 0 0 0 432 1 0 Bit 23 to 20 L1PB (L1 layer Palette Base) Shows the value added to the index when subtracting palette of L1 layer. 16 times of setting value is added. Bit 31 to 30 L1EC (L1 layer Extended Color mode) Sets extended color mode for L1 layer 00 01 1x Mode determined by L0C Direct color (24 bits/pixel) mode Reserved L1DA (L1 layer Display Address) Register DisplayBaseAddress + 34H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0DA R/W R0 RW Initial value 0 Don't care This register sets the display origin address of the L1 layer. For the direct color mode (16 bits/pixel), the lower 1 bit is "0", and this register is treated as being aligned in 2 bytes. Wraparound processing is not performed for the L1 layer, so the frame origin linear address and display position (X coordinates, and Y coordinates) are not specified. L1WX (L1 layer Window position X) Register DisplayBaseAddress + 124H (DispplayBaseAddress + 18H) address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WX R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 This register sets the X coordinates of the display position of the L1 layer window. This register is placed in two address spaces. The parenthesized address is the register address to maintain compatibility with previous products. The same applies to L1WY, L1WW, and L1WH. L1WY (L1 layer Window position Y) Register DisplayBaseAddress + 126H (DispplayBaseAddress + 1AH) address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WY R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 This register sets the Y coordinates of the display position of the L1 layer window. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 171 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L1WW (L1 layer Window Width) Register DisplayBaseAddress + 128H (DispplayBaseAddress + 1CH) address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WW R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 This register controls the horizontal direction display size ( idth) of the L1 layer w w indow. specify "0". L1WH (L1 layer Window Height) Register DisplayBaseAddress + 1 2AH ((DisplayBaseAddress + 1 EH) address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WH R/W R0 RW Initial value 0 Don't care Do not 4 3 2 1 0 This register controls the vertical direction display size (height) of the L1 layer window. Setting value + 1 is the height. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 172 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L2M (L2 layer Mode) Register DisplayBaseAddress + 40H address Bit number 31 30 29 28 27 - - 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L2C L2FLP Reserved L2W Reserved L2H R/W RW RW R0 RW R0 RW Initial value 0 00 0 Don't care 0 Don't care Bit 11 to 0 L2H (L2 layer Height) Specifies the height of the logic frame of the L2 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L2W (L2 layer memory Width) Sets the memory width (stride) of the logic frame of the L2 layer in 64-byte units Bit 30 and 29 L2FLP (L2 layer Flip mode) Sets flipping mode for L2 layer 00 01 10 11 Displays frame 0 Displays frame 1 Switches frame 0 and 1 alternately for display Reserved Bit 31 L2C (L2 layer Color mode) Sets the color mode for L2 layer 0 1 Indirect color (8 bits/pixel) mode Direct color (16 bits/pixel) mode MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 173 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L2EM (L2 layer Extended Mode) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 130H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 L2EC Reserved L2PB Reserved RW R0 RW R0 00 0 0 0 ----432 1 0 L2OM L0WP RW RW 0 Bit 0 L2 WP (L2 layer Window Position enable) Selects the display position of L2 layer 0 1 Compatibility mode display (ML layer supported) Window display Bit 1 L2OM (L2 layer Overlay Mode) Selects the overlay mode for L2 layer 0 1 Compatibility mode Extended mode Bit 23 to 20 L2PB (L2 layer Palette Base) Shows the value added to the index when subtracting palette of L2 layer. 16 times of setting value is added. Bit 31 and 30 L2EC (L2 layer Extended Color mode) Sets extended color mode for L2 layer 00 01 1x Mode determined by L2C Direct color (24 bits/pixel) mode Reserved MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 174 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L2OA0 (L2 layer Origin Address 0) Register DisplayBaseAddress + 44 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L2 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L2DA0 (L2 layer Display Address 0) Register DisplayBaseAddress + 48H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L2 layer in frame 0. bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L2OA1 (L2 layer Origin Address 1) For the direct color mode (16 Register DisplayBaseAddress + 4CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L2 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L2DA1 (L2 layer Display Address 1) Register DisplayBaseAddress + 50H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L2 layer in frame 1. bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L2DX (L2 layer Display position X) Register DisplayBaseAddress + 54H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 For the direct color mode (16 9 8 7 6 5 L2DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L2 layer on the basis of the origin of the logic frame in pixels. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 175 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L2DY (L2 layer Display position Y) Register DisplayBaseAddress + 56H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L2 layer on the basis of the origin of the logic frame in pixels. L2WX (L2 layer Window position X) Register DisplayBaseAddress + 134H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WX RW Don't care 4 3 2 1 0 This register sets the X coordinates of the display position of the L2 layer window. L2WY (L2 layer Window position Y) Register DisplayBaseAddress + 136H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WY RW Don't care 4 3 2 1 0 This register sets the Y coordinates of the display position of the L2 layer window. L2WW (L2 layer Window Width) Register DisplayBaseAddress + 138H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WW RW Don't care 4 3 2 1 0 This register controls the horizontal direction display size (width) of the L2 layer window. specify "0". L2WH (L2 layer Window Height) Register DisplayBaseAddress + 1 3AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 Do not 9 8 7 6 5 L2WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L2 layer window. Setting value + 1 is the height. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 176 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L3M (L3 layer Mode) Register DisplayBaseAddress + 58H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L3C L3FLP Reserved L3W Reserved L3H R/W RW R0 R0 RW R0 RW Initial value 0 0 0 Don't care 0 Don't care Bit 11 to 0 L3H (L3 layer Height) Specifies the height of the logic frame of the L3 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L3W (L3 layer memory Width) Sets the memory width (stride) of the logic frame of the L3 layer in 64-byte units Bit 30 and 29 L3FLP (L3 layer Flip mode) Sets flipping mode for L3 layer 00 01 10 11 Displays frame 0 Displays frame 1 Switches frame 0 and 1 alternately for display Reserved Bit 31 L3C (L3 layer Color mode) Sets the color mode for L3 layer 0 1 Indirect color (8 bits/pixel) mode Direct color (16 bits/pixel) mode MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 177 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L3EM (L3 layer Extended Mode) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 140H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 L3EC Reserved L3PB Reserved RW 00 R0 0 RW 0 R0 0 --- 432 1 0 L3OM L3WP RW RW 0 0 Bit 0 L3 WP (L3 layer Window Position enable) Selects the display position of L3 layer 0 1 Compatibility mode display (MR layer supported) Window display Bit 1 L3OM (L3 layer Overlay Mode) Selects the overlay mode for L3 layer 0 1 Compatibility mode Extended mode Bit 23 to 20 L3PB (L3 layer Palette Base) Shows the value added to the index when subtracting palette of L3 layer. 16 times of setting value is added. Bit 31 and 30 L3EC (L3 layer Extended Color mode) Sets extended color mode for L3 layer 00 01 1x Mode determined by L3C Direct color (24 bits/pixel) mode Reserved MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 178 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L3OA0 (L3 layer Origin Address 0) Register DisplayBaseAddress + 5CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L3 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L3DA0 (L3 layer Display Address 0) Register DisplayBaseAddress + 60H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L3 layer in frame 0. bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L3OA1 (L3 layer Origin Address 1) For the direct color mode (16 Register DisplayBaseAddress + 64H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L3 layer in frame 1. are fixed to "0", this address is 16-byte aligned. L3OA1 (L3 layer Display Address 1) Since lower 4-bits Register DisplayBaseAddress + 68H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L3 layer in frame 1. bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L3DX (L3 layer Display position X) Register DisplayBaseAddress + 6CH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 For the direct color mode (16 9 8 7 6 5 L3DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L3 layer on the basis of the origin of the logic frame in pixels. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 179 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L3DY (L3 layer Display position Y) Register DisplayBaseAddress + 6EH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L3 layer on the basis of the origin of the logic frame in pixels. L3WX (L3 layer Window position X) Register DisplayBaseAddress + 144H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WX RW Don't care 4 3 2 1 0 This register sets the X coordinates of the display position of the L3 layer window. L3WY (L3 layer Window position Y) Register DisplayBaseAddress + 146H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WY RW Don't care 4 3 2 1 0 This register sets the Y coordinates of the display position of the L3 layer window. L3WW (L3 layer Window Width) Register DisplayBaseAddress + 148H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WW RW Don't care 4 3 2 1 0 This register controls the horizontal direction display size ( idth) of the L3 layer window. w specify "0". L3WH (L3-layer Window Height) Register DisplayBaseAddress + 1 4AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 Do not 9 8 7 6 5 L3WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L3 layer window. Setting value + 1 is the height. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 180 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L4M (L4 layer Mode) Register DisplayBaseAddress + 70H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L4C L4FLP Reserved L4W Reserved L4H R/W RW RW R0 RW R0 RW Initial value 0 Don't care 0 Don't care Bit 11 to 0 L4H (L4 layer Height) Specifies the height of the logic frame of the L4 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L4W (L4 layer memory Width) Sets the memory width (stride) logic frame of the L4 layer in 64-byte units Bit 30 and 29 L4FLP (L4 layer Flip mode) Sets flipping mode for L4 layer 00 01 10 11 Displays frame 0 Displays frame 1 Switches frame 0 and 1 alternately for display Reserved Bit 31 L4C (L4 layer Color mode) Sets the color mode for L4 layer 0 1 Indirect color (8 bits/pixel) mode Direct color (16 bits/pixel) mode MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 181 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L4EM (L4 layer Extended Mode) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 150H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 L4EC Reserved RW 00 R0 0 RW 0 R0 0 --- 432 1 0 L4OM L4WP RW RW 0 0 Bit 0 L4 WP (L4 layer Window Position enable) Selects the display position of L4 layer 0 1 Compatibility mode display (BL layer supported) Window display Bit 1 L4OM (L4 layer Overlay Mode) Selects the overlay mode for L4 layer 0 1 Compatibility mode Extended mode Bit 23 to 20 L4PB (L4 layer Palette Base) Shows the value added to the index when subtracting palette of L4 layer. 16 times of setting value is added. Bit 31 and 30 L4EC (L4 layer Extended Color mode) Sets extended color mode for L4 layer 00 01 1x Mode determined by L4C Direct color (24 bits/pixel) mode Reserved MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 182 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L4OA0 (L4 layer Origin Address 0) Register DisplayBaseAddress + 74H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L4 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L4DA0 (L4 layer Display Address 0) Register DisplayBaseAddress + 78H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L4 layer in frame 0. bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L4OA1 (L4 layer Origin Address 1) For the direct color mode (16 Register DisplayBaseAddress + 7CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L4 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L4OA1 (L4 layer Display Address 1) Register DisplayBaseAddress + 80H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L4 layer in frame 1. bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L4DX (L4 layer Display position X) Register DisplayBaseAddress + 84H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 For the direct color mode (16 9 8 7 6 5 L4DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L4 layer on the basis of the origin of the logic frame in pixels. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 183 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L4DY (L4 layer Display position Y) Register DisplayBaseAddress + 86H addres s Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L4 layer on the basis of the origin of the logic frame in pixels. L4WX (L4 layer Window position X) Register DisplayBaseAddress + 154H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WX RW Don't care 4 3 2 1 0 This register sets the X coordinates of the display position of the L4 layer window. L4WY (L4 layer Window position Y) Register DisplayBaseAddress + 156H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WY RW Don't care 4 3 2 1 0 This register sets the Y coordinates of the display position of the L4 layer window. L4WW (L4 layer Window Width) Register DisplayBaseAddress + 158H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WW RW Don't care 4 3 2 1 0 This register controls the horizontal direction display size ( idth) of the L4 layer window. w specify "0". L4WH (L4 layer Window Height) Register DisplayBaseAddress + 1 5AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 Do not 9 8 7 6 5 L4WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L4 layer window. Setting value + 1 is the height. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 184 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L5M (L5 layer Mode) Register DisplayBaseAddress + 88H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L5C L5FLP Reserved L5W Reserved L5H R/W RW RW R0 RW R0 RW Initial value 0 Don't care 0 Don't care Bit 11 to 0 L5H (L5 layer Height) Specifies the height of the logic frame of the L5 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L5W (L5 layer memory Width) Sets the memory width (stride) logic frame of the L5 layer in 64-byte units Bit 30 and 29 L5FLP (L5 layer Flip mode) Sets flipping mode for L5 layer 00 01 10 11 Displays frame 0 Displays frame 1 Switches frame 0 and 1 alternately for display Reserved Bit 31 L5C (L5 layer Color mode) Sets the color mode for L5 layer 0 1 Indirect color (8 bits/pixel) mode Direct color (16 bits/pixel) mode MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 185 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L5EM (L5 layer Extended Mode) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 160H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 L5EC Reserved RW 00 R0 0 --- 432 1 0 L5OM L5WP RW RW 0 Bit 0 L5 WP (L5 layer Window Position enable) Selects the display position of L5 layer 0 1 Compatibility mode display (BR layer supported) Window display Bit 1 L5OM (L5 layer Overlay Mode) Selects the overlay mode for L5 layer 0 1 Compatibility mode Extended mode Bit 31 to 30 L5EC (L5 layer Extended Color mode) Sets extended color mode for L5 layer 00 01 1x Mode determined by L5C Direct color (24 bits/pixel) mode Reserved MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 186 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L5OA0 (L5 layer Origin Address 0) Register DisplayBaseAddress + 8CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L5 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L5DA0 (L5 layer Display Address 0) Register DisplayBaseAddress + 90H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L5 layer in frame 0. bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L5OA1 (L5 layer Origin Address 1) For the direct color mode (16 Register DisplayBaseAddress + 94H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L5 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L5OA1 (L5 layer Display Address 1) Register DisplayBaseAddress + 98H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L5 layer in frame 1. bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L5DX (L5 layer Display position X) Register DisplayBaseAddress + 9CH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 For the direct color mode (16 9 8 7 6 5 L5DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L5 layer on the basis of the origin of the logic frame in pixels. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 187 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L5DY (L5 layer Display position Y) Register DisplayBaseAddress + 9E H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L5 layer on the basis of the origin of the logic frame in pixels. L5WX (L5 layer Window position X) Register DisplayBaseAddress + 164H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WX RW Don't care 4 3 2 1 0 This register sets the X coordinates of the display position of the L5 layer window. L5WY (L5 layer Window position Y) Register DisplayBaseAddress + 166H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WY RW Don't care 4 3 2 1 0 This register sets the Y coordinates of the display position of the L5 layer window. L5WW (L5 layer Window Width) Register DisplayBaseAddress + 168H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WW RW Don't care 4 3 2 1 0 This register controls the horizontal direction display size ( idth) of the L5 layer window. w specify "0". L5WH (L5 layer Window Height) Register DisplayBaseAddress + 1 6AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 Do not 9 8 7 6 5 L5WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L5 layer window. Setting value + 1 is the height. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 188 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CUTC (Cursor Transparent Control) Register DisplayBaseAddress + A0H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 CUZT RW Don't care 7 6 5 4 3 CUTC RW Don't care 2 1 0 Bit 7 to 0 CUTC (Cursor Transparent Code) Sets color code handled as transparent code Bit 8 CUZT (Cursor Zero Transparency) Defines handling of color code 0 0 1 Code 0 as transparency color Code 0 as non-transparency color CPM (Cursor Priority Mode) Register DisplayBaseAddress + A2 H address Bit number 7 6 5 Bit field name Reserved CEN1 R/W R0 RW Initial value 0 0 4 CEN0 RW 0 3 Reserved R0 0 2 1 CUO1 RW 0 0 CUO0 RW 0 This register controls the display priority of cursors. Cursor 0 is always preferred to cursor 1. Bit 0 CUO0 (Cursor Overlap 0) Sets display priority between cursor 0 and pixels of Console layer 0 1 Puts cursor 0 at lower than L0 layer. Puts cursor 0 at higher than L0 layer. Bit 1 CUO1 (Cursor Overlap 1) Sets display priority between cursor 1 and C layer 0 1 Puts cursor 1 at lower than L0 layer. Puts cursor 1 at lower than L0 layer. Bit 4 CEN0 (Cursor Enable 0) Sets enabling display of cursor 0 0 1 Disabled Enabled Bit 5 CEN1 (Cursor Enable 1) Sets enabling display of cursor 1 0 1 Disabled Enabled MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 189 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CUOA0 (Cursor-0 Origin Address) Register DisplayBaseAddress + A4 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CUOA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the start address of the cursor 0 pattern. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. CUX0 (Cursor-0 X position) Register DisplayBaseAddress + A8 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 CUX0 RW Don't care 4 3 2 1 0 This register sets the display position (X coordinates) of the cursor 0 in pixels. The reference position of the coordinates is the top left of the cursor pattern. CUY0 (Cursor-0 Y position) Register DisplayBaseAddress + Aa H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 CUY0 RW Don't care 4 3 2 1 0 This register sets the display position (Y coordinates) of the cursor 0 in pixels. The reference position of the coordinates is the top left of the cursor pattern. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 190 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CUOA1 (Cursor-1 Origin Address) Register DisplayBaseAddress + AC H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CUOA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the start address of the cursor 1 pattern. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. CUX1 (Cursor-1 X position) Register DisplayBaseAddress + B0H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 CUX1 RW Don't care 4 3 2 1 0 This register sets the display position (X coordinates) of the cursor 1 in pixels. The reference position of the coordinates is the top left of the cursor pattern. CUY1 (Cursor-1 Y position) Register DisplayBaseAddress + B2H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 CUY1 RW Don't care 4 3 2 1 0 This register sets the display position (Y coordinates) of the cursor 1 in pixels. The reference position of the coordinates is the top left of the cursor pattern. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 191 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DLS (Display Layer Select) Register DisplayBaseAddress + 180H address Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved DLS5 DLS4 DLS3 DLS2 DLS1 DSL0 R/W R0 R0 RW R0 RW R0 RW R0 RW R0 RW R0 RW Initial value 101 100 011 010 001 000 This register defines the blending sequence. Bit 3 to 0 DSL0 (Display Layer Select 0) Selects the top layer subjected to blending. 0000 0001 : 0101 0110 : 0110 0111 L0 layer L1 layer : L5 layer Reserved : Reserved Not selected Bit 7 to 4 DSL1 (Display Layer Select 1) Selects the second layer subjected to blending. The bit values are the same as DSL0. Bit 11 to 8 DSL2 (Display Layer Select 2) Selects the third layer subjected to blending. The bit values are the same as DSL0. Bit 15 to 12 DSL3 (Display Layer Select 3) Selects the fourth layer subjected to blending. The bit values are the same as DSL0. Bit 19 to 16 DSL4 (Display Layer Select 4) Selects the fifth layer subjected to blending. The bit values are the same as DSL0. Bit 23 to 20 DSL5 (Display Layer Select 5) Selects the bottom layer subjected to blending. The bit values are the same as DSL0. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 192 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DBGC (Display Background Color) Register DisplayBaseAddress + 184H address Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved DBGR DBGG DBGB R/W R0 Initial value This register specifies the color to be displayed in areas outside the display area of each layer on the window. Bit 7 to 0 DBGB (Display Background Blue) Specifies the blue level of the background color. Bit 15 to 8 DBGG (Display Background Green) Specifies the green level of the background color. Bit 23 to 16 DBGR (Display Background Red) Specifies the red level of the background color. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 193 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L0BLD (L0 Blend) Register DisplayBaseAddress + B4H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0BE L0BS L0BI L0BP Reserved L0BR R/W R0 RW RW RW RW R0 RW Initial value 0 0 0 0 0 This register specifies the blend parameters for the L0 layer. This register corresponds to BRATIO or BMODE for previous products. Bit 7 to 0 L0BR (L0 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L0BP (L0 layer Blend Plane) Specifies that the L5 layer is the blend plane. 0 1 Value of L0BR used as blend ratio Pixel of L5 layer used as blend ratio Bit 14 L0BI (L0 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". 0 1 Blend ratio calculated as is 1/256 added when blend ratio 0 Bit 15 L0BS (L0 layer Blend Select) Selects the blend calculation expression. 0 1 Upper image x Blend ratio + Lower image x (1 - Blend ratio) Upper image x (1 - Blend ratio) + Lower image x Blend ratio Bit 16 L0BE (L0 layer Blend Enable) This bit enables blending. 0 1 Overlay via transparent color Overlay via blending Before blending, the blend mode must be specified using L0BE, and alpha must also be enabled for L0 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 194 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L1BLD (L1 Blend) Register DisplayBaseAddress + 188H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L1BE L1BS L1BI L1BP Reserved L1BR R/W R0 RW RW RW RW R0 RW Initial value 0 0 0 0 0 This register specifies the blend parameters for the L1 layer. Bit 7 to 0 L1BR (L1 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L1BP (L1 layer Blend Plane) Specifies that the L5 layer is the blend plane. 0 1 Value of L1BR used as blend ratio Pixel of L5 layer used as blend ratio Bit 14 L1BI (L1 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". 0 1 Blend ratio calculated as is 1/256 added when blend ratio 0 Bit 15 L1BS (L1 layer Blend Select) Selects the blend calculation expression. 0 1 Upper image x Blend ratio + Lower image x (1 - Blend ratio) Upper image x (1 - Blend ratio) + Lower image x Blend ratio Bit 16 L1BE (L1 layer Blend Enable) This bit enables blending. 0 1 Overlay via transparent color Overlay via blending Before blending, the blend mode must be specified using L1BE, and alpha must also be enabled for L1 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 195 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L2BLD (L2 Blend) Register DisplayBaseAddress + 18CH address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2BE L2BS L2BI L2BP Reserved L2BR R/W R0 RW RW RW RW R0 RW Initial value 0 0 0 0 0 This register specifies the blend parameters for the L2 layer. Bit 7 to 0 L2BR (L2 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L2BP (L2 layer Blend Plane) Specifies that the L5 layer is the blend plane. 0 1 Value of L2BR used as blend ratio Pixel of L5 layer used as blend ratio Bit 14 L2BI (L2 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". 0 1 Blend ratio calculated as is 1/256 added when blend ratio 0 Bit 15 L2BS (L2 layer Blend Select) Selects the blend calculation expression. 0 1 Upper image x Blend ratio + Lower image x (1 - Blend ratio) Upper image x (1 - Blend ratio) + Lower image x Blend ratio Bit 16 L2BE (L2 layer Blend Enable) This bit enables blending. 0 1 Overlay via transparent color Overlay via blending Before blending, the blend mode must be specified using L2BE, and alpha must also be enabled for L2 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 196 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L3BLD (L3 Blend) Register DisplayBaseAddress + 190H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3BE L3BS L3BI L3BP Reserved L3BR R/W RW Rw RW RW RW Initial value 0 0 0 0 0 This register specifies the blend parameters for the L3 layer. Bit 7 to 0 L3BR (L3 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L3BP (L3 layer Blend Plane) Specifies that the L5 layer is the blend plane. 0 1 Value of L3BR used as blend ratio Pixel of L5 layer used as blend ratio Bit 14 L3BI (L3 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". 0 1 Blend ratio calculated as is 1/256 added when blend ratio 0 Bit 15 L3BS (L3 layer Blend Select) Selects the blend calculation expression. 0 1 Upper image x Blend ratio + Lower image x (1 - Blend ratio) Upper image x (1 - Blend ratio) + Lower image x Blend ratio Bit 16 L3BE (L3 layer Blend Enable) This bit enables blending. 0 1 Overlay via transparent color Overlay via blending Before blending, the blend mode must be specified using L3BE, and alpha must also be enabled for L3 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 197 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L4BLD (L4 Blend) Register DisplayBaseAddress + 194H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4BE L4BS L4BI L4BP Reserved L4BR R/W R0 RW RW RW RW R0 RW Initial value 0 0 0 0 0 This register specifies the blend parameters for the L4 layer. Bit 7 to 0 L4BR (L4 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L4BP (L4 layer Blend Plane) Specifies that the L5 layer is the blend plane. 0 1 Value of L4BR used as blend ratio Pixel of L5 layer used as blend ratio Bit 14 L4BI (L4 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". 0 1 Blend ratio calculated as is 1/256 added when blend ratio 0 Bit 15 L4BS (L4 layer Blend Select) Selects the blend calculation expression. 0 1 Upper image x Blend ratio + Lower image x (1 - Blend ratio) Upper image x (1 - Blend ratio) + Lower image x Blend ratio Bit 16 L4BE (L4 layer Blend Enable) This bit enables blending. 0 1 Overlay via transparent color Overlay via blending Before blending, the blend mode must be specified using L4BE, and alpha must also be enabled for L4 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 198 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L5BLD (L5 Blend) Register DisplayBaseAddress + 198h address Bit number 31 30 29 28 ----- 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5BE L5BS L5BI Reserved L5BR R/W R0 RW RW RW R0 RW Initial value 0 0 0 This register specifies the blend parameters for the L5 layer. Bit 7 to 0 L5BR (L5 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 14 L5BI (L5 layer Blend Increment) Selects whether or not 1/256 is added when th e blend ratio is not "0". 0 1 Blend ratio calculated as is 1/256 added when blend ratio 0 Bit 15 L5BS (L5 layer Blend Select) Selects the blend calculation expression. 0 1 Upper image x Blend ratio + Lower image x (1 - Blend ratio) Upper im age x (1 - Blend ratio) + Lower image x Blend ratio Bit 16 L5BE (L5 layer Blend Enable) This bit enables blending. 0 1 Overlay via transparent color Overlay via blending Before blending, the blend mode must be specified using L5BE, and alpha must also be enabled for L5 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 199 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L0TC (L0 layer Transparency Control) Register DisplayBaseAddress + BCH address Bit number 15 14 13 12 11 10 Bit field name L0ZT R/W RW Initial value 0 9 8 7 L0TC RW 0 6 5 4 3 2 1 0 This register sets the transparent color for the L0 layer. Color set by this register is transparent in blend mode. When L0TC = 0 and L0ZT = 0, color 0 is displayed in black (transparent). This register corresponds to the CTC register for previous products. Bit 14 to 0 L0TC (L0 layer Transparent Color) Sets transparent color code for the L0 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 15 L0ZT (L0 layer Zero Transparency) Sets handling of color code 0 in L0 layer 0: 1: Code 0 as transparency color Code 0 as non-transparency color L2TC (L2 layer Transparency Control) Register DisplayBaseAddress + C2H address Bit number 15 14 13 12 11 10 Bit field name L2ZT R/W RW Initial value 0 9 8 7 L2TC RW 0 6 5 4 3 2 1 0 This register sets the transparent color for the L2 layer. When L2TC = 0 and L2ZT = 0, color 0 is displayed in black (transparent). This register corresponds to the MLTC register for previous products. Bit 14 to 0 L2TC (L2 layer Transparent Color) Sets transparent color code for the L2 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 15 L2ZT (L2 layer Zero Transparency) Sets handling of color code 0 in L2 layer 0 1 Code 0 as transparency color Code 0 as non-transparency color MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 200 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L3TC (L3 layer Transparency Control) Register DisplayBaseAddress + C0H address Bit number 15 14 13 12 11 10 Bit field name L3ZT R/W RW Initial value 0 9 8 7 L3TC RW 0 6 5 4 3 2 1 0 This register sets the transparent color for the L3 layer. When L3TC = 0 and L3ZT = 0, color 0 is displayed in black (transparent). This register corresponds to the MLTC register for previous products. Bit 14 to 0 L3TC (L3 layer Transparent Color) Sets transparent color code for the L3 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 15 L3ZT (L3 layer Zero Transparency) Sets handling of color code 0 in L3 layer 0 1 Code 0 as transparency color Code 0 as non-transparency color L0ETC (L0 layer Extend Transparency Control) Register DisplayBaseAddress + 1A0 H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L0ETZ Reserved L0TEC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L0 layer. The 24 bits/pixel transparent color is set using this register. The lower 15 bits of this register are physically the same as L0TC. Also, L0ETZ is physically the same as L0TZ. When L0ETC = 0 and L0EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L0ETC (L0 layer Extend Transparent Color) Sets transparent color code for the L0 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L0EZT (L0 layer Extend Zero Transparency) Sets handling of color code 0 in L0 layer 0 1 Code 0 as transparency color Code 0 as non-transparency color MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 201 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L1ETC (L1 layer Extend Transparency Control) Register DisplayBaseAddress + 1A4 H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L1ETZ Reserved L1TEC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L1 layer. When L1ETC = 0 and L1EZT = 0, color 0 is displayed in black (transparent). For YCbCr display, transparent color checking is not performed; processing is always performed assuming that transparent color is not used. Bit 23 to 0 L1ETC (L1 layer Extend Transparent Color) Sets transparent color code for the L1 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L1EZT (L1 layer Extend Zero Transparency) Sets handling of color code 0 in L1 layer 0 1 Code 0 as transparency color Code 0 as non-transparency color L2ETC (L2 layer Extend Transparency Control) Register DisplayBaseAddress + 1A8 H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L2ETZ Reserved L2TEC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L2 layer. The 24 bits/pixel transparent color is set using this register. The lower 15 bits of this register are physically the same as L2TC. Also, L2ETZ is physically the same as L2TZ. When L2ETC = 0 and L2EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L2ETC (L2 layer Extend Transparent Color) Sets transparent color code for the L2 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L2EZT (L2 layer Extend Zero Transparency) Sets handling of color code 0 in L2 layer 0 1 Code 0 as transparency color Code 0 as non-transparency color MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 202 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L3ETC (L3 layer Extend Transparency Control) Register DisplayBaseAddress + 1AC H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L3ETZ Reserved L3TEC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L3 layer. The 24 bits/pixel transparent color is set using this register. The lower 15 bits of this register are physically the same as L3TC. Also, L3ETZ is physically the same as L3TZ. When L3ETC = 0 and L3EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L3ETC (L3 layer Extend Transparent Color) Sets transparent color code for the L3 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L3EZT (L3 layer Extend Zero Transparency) Sets handling of color code 0 in L3 layer 0 1 Code 0 as transparency color Code 0 as non-transparency color L4ETC (L4 layer Extend Transparency Control) Register DisplayBaseAddress + 1B0H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L4ETZ Reserved L4TEC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L4 layer. This register sets the transparent color for the L4 layer. When L4ETC = 0 and L4EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L4ETC (L4 layer Extend Transparent Color) Sets transparent color code for the L4 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L4EZT (L4 layer Extend Zero Transparency) Sets handling of color code 0 in L4 layer 0 1 Code 0 as transparency color Code 0 as non-transparency color MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 203 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L5ETC (L5 layer Extend Transparency Control) Register DisplayBaseAddress + 1B4H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L5ETZ Reserved L5TEC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L5 layer. This register sets the transparent color for the L5 layer. When L5ETC = 0 and L5EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L5ETC (L5 layer Extend Transparent Color) Sets transparent color code for the L5 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L5EZT (L5 layer Extend Zero Transparency) Sets handling of color code 0 in L5 layer 0 1 Code 0 as transparency color Code 0 as non-transparency color MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 204 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L0PAL0-255 (L0 layer Palette 0-255) Register DisplayBaseAddress + 400H -- DisplayBaseAddress + 7FFH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R G B R/W RW R0 RW R0 RW R0 RW R0 Initial value Don't care 0000000 Don't care 00 Don't care 00 Don't care 00 These are color palette registers for L0 layer and cursors. In the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. This register corresponds to the CPALn register for previous products. Bit 7 to 2 B (Blue) Sets blue color component Bit 15 to 10 G (Green) Sets green color component Bit 23 to 18 R (Red) Sets red color component Bit 31 A (Alpha) Specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 1 Blending not performed even when blending mode enabled Overlay is performed via transparent color. Blending performed MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 205 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L1PAL0-255 (L1 layer Palette 0-255) Register DisplayBaseAddress + 800H -- DisplayBaseAddress + BFFH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R G B R/W RW R0 RW R0 RW R0 RW R0 Initial value Don't care 0000000 Don't care 00 Don't care 00 Don't care 00 These are color palette registers for L1 layer and cursors. In the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. This register corresponds to the MBPALn register for previous products. Bit 7 to 2 B (Blue) Sets blue color component Bit 15 to 10 G (Green) Sets green color component Bit 23 to 18 R (Red) Sets red color component Bit 31 A (Alpha) Specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 1 Blending not performed even when blending mode enabled Overlay is performed via transparent color. Blending performed MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 206 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L2PAL0-255 (L2 layer Palette 0-255) Register DisplayBaseAddress + 1000H -- DisplayBaseAddress + 13FFH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R G B R/W RW R0 RW R0 RW R0 RW R0 Initial value Don't care 0000000 Don't care 00 Don't care 00 Don't care 00 These are color palette registers for L2 layer and cursors. In the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. Bit 7 to 2 B (Blue) Sets blue color component Bit 15 to 10 G (Green) Sets green color component Bit 23 to 18 R (Red) Sets red color component Bit 31 A (Alpha) Specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 1 Blending not performed even when blending mode enabled Overlay is performed via transparent color. Blending performed MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 207 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL L3PAL0-255 (L3 layer Palette 0-255) Register DisplayBaseAddress + 1400H -- DisplayBaseAddress + 17FFH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R G B R/W RW R0 RW R0 RW R0 RW R0 Initial value Don't care 0000000 Don't care 00 Don't care 00 Don't care 00 These are color palette registers for L3 layer and cursors. In the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. Bit 7 to 2 B (Blue) Sets blue color component Bit 15 to 10 G (Green) Sets green color component Bit 23 to 18 R (Red) Sets red color component Bit 31 A (Alpha) Specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 1 Blending not performed even when blending mode enabled Overlay is performed via transparent color. Blending performed MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 208 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.4 Video Capture Registers VCM (Video Capture Mode) Register CaputureBaseAddress + 00H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name VIE VIS| R/W RW RW| Initial value 0 Reserved RX X CM Reserved VI RW RX RW 00 X 0 Reserved RX X VS Rsv RW RX 0X This register sets the video capture mode. Bit 31 VIE (Video Input Enable) Enables video capture function 0: 1: Bit 30 Does not capture video Captures video VIS (Video Input Select) 0 1 RBT656 RGB666 Bit 25 to 24 CM (Capture Mode) Sets video capture mode To capture vides, set these bits to "11". 00: 01: 10: 11: Initial value Reserved Reserved Capture Bit 20 VI (Vertical Interpolation) Sets whether to perform vertical interpolation 0: 1: Performs vertical interpolation The graphics are enlarged vertically by two times Does not perform vertical interpolation Bit 1 VS (Video Select) Selects NTSC or PAL 0: 1: NTSC PAL MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 209 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CSC (Capture SCale) Register address Bit number Bit field name CaputureBaseAddress + 04H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VSCI VSCF HSCI HSCF RW RW RW RW 00001 00000000000 00001 00000000000 R/W Initial value This register sets the video capture enlargement/reduction ratio. Bit 31 to 27 VSCI (Vertical SCale Integer) Sets integer part of vertical enlargement/reduction ratio Bit 26 to 16 VSCF (Vertical Scale Fraction) Sets fraction part of vertical enlargement/reduction ratio Bit 15 to 11 HSCI (Horizontal SCale Integer) Sets integer part of horizontal enlargement/reduction ratio Bit 10 to 0 HSCF (Horizontal SCale Fraction) Sets fraction part of horizontal enlargement/reduction ratio VCS (Video Capture Status) Register CaputureBaseAddress + 08H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name R/W Initial value Reserved RX Don't care CE RW 00000 This register indicates the ITU-RBT656 SAV and EAV status. To detect error codes, set NTSC/PAL in the VS bit of VCM. If NTSC is set, reference the number of data in the capture data count register (CDCN). If PAL is set, reference the number of data in the capture data counter register (CDCP). If the reference data does not match the stream data , or undefined Fourth word of SAV/EAV codes are detected, bits 4 to 0 of the video capture status register (VCS) will be values as follows. Bits 4-0 CE (Capture Error) Indicates error occurred during video capture Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 1 : : : : : RBT.656 RBT.656 RBT.656 RBT.656 RBT.656 H code error (End) H code error (Start) undefined error (Code Bit7-0) undefined error (Code Bit7-4) undefined error (Code Bit7) 0 : true 0 : true 0 : true 0 : true 0 : true MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 210 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CBM (vide Capture Buffer Mode) Register address Bit # CaputureBaseAddress + 10H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name 00 Reserved CBW Reserved R/W RW RX RW Rx Initial value Don't care Don't care Don't care Bit 23 to 16 CBW (Capture Buffer memory Width) Sets memory width (stride) of capture buffer in 64 bytes Bit 31 OO (Odd Only mode) Specifies whether to capture odd fields only 0: 1: Normal mode Odd only mode CBOA (video Capture Buffer Origin Address) Register address Bit number Bit field name CaputureBaseAddress + 14H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CBOA RX RW R0 Don't care Don't care 0 R/W Initial value This register specifies the starting (origin) address of the video capture buffer. CBLA (video Capture Buffer Limit Address) Register address Bit number Bit field name CaputureBaseAddress + 18H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CBLA RX RW R0 Don't care Don't care 0 R/W Initial value This register specifies the end (limit) address of the video capture buffer. CBLA must be larger than CBOA. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 211 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CIHSTR (Capture Image Horizontal STaRt) Register address Bit number Bit field name CaputureBaseAddress + 1CH 15 14 13 12 Reserved RX Don't care 11 10 9 8 7 6 5 4 CIHSTR RW Don't care 3 2 1 0 R/W Initial value This register sets the range of the images to be written (captured) to the video capture buffer. Specify the X coordinates located in the top left of the image range as the count of pixels from the top left of the image. For reduction, apply this setting to the post-reduction image coordinates. CIVSTR (Capture Image Vertical STaRt) Register address Bit number Bit field name CaputureBaseAddress + 1EH 15 14 13 12 Reserved RX Don't care 11 10 9 8 7 6 5 4 CIVSTR RW Don't care 3 2 1 0 R/W Initial value This register sets the range of the images to be written (captured) to the video capture buffer. Specify the Y coordinates located in the top left of the image range as the count of pixels from the top left of the image. For reduction, apply this setting to the post-reduction image coordinates. CIHEND (Capture Image Horizontal END) Register address Bit number Bit field name CaputureBaseAddress + 20H 15 14 13 12 Reserved RX Don't care 11 10 9 8 7 6 5 4 CIHEND RW Don't care 3 2 1 0 R/W Initial value This register sets the range of the images to be written (captured) to the video capture buffer. Specify the X coordinates located in the bottom right of the image range as the count of pixels from the top left of the image. For reduction, apply this setting to the post-reduction image coordinates. If the pixel at the right end of the image is not aligned on 64 bits/word boundary, extra data is written before 64 bits/word boundary. If the width of the input image is less than the range set by this command, data is written only at the size of input image. CIVEND (Capture Image Vertical END) Register address Bit number Bit field name CaputureBaseAddress + 22H 15 14 13 12 Reserved RX Don't care 11 10 9 8 7 6 5 4 CIVEND RW Don't care 3 2 1 0 R/W Initial value This register sets the range of the images to be written (captured) to the video capture buffer. Specify the Y coordinates located in the bottom right of the image range as the count of pixels from the top left of the original image to be input. For reduction, apply this setting to the post-reduction image coordinates. If the count of rasters of the input image is less than the range set by this command, data is written only at the size of the input image. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 212 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CHP (Capture Horizontal Pixel) Register address Bit number Bit field name CaputureBaseAddress + 28H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHP RX RW X 168H (360D) R/W Initial value This register sets the count of horizontal pixels of the image output after scaling. Specify the count of horizontal pixels in 2 pixels. CVP (Capture Vertical Pixel) Register address Bit number Bit field name CaputureBaseAddress + 2cH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CVPP Reserved CVPN RX RW RX RW X 271H (625D) X 20DH (525D) R/W Initial value This register sets the count of vertical pixels of the image output after scaling. The fields to be used depend on the video format to be used. Bit 25 to 16 CVPP (Capture Vertical Pixel for PAL) Set count of vertical pixels of output image in PAL format used Bit 9 to 0 CVPN (Capture Vertical Pixel for NTSC) Set count of vertical pixels of output image in NTSC format used MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 213 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CLPF (Capture Low Pass Filter) Register CaputureBaseAddress + 40H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserve CVLPF Reserve CHLPF Reserve R/W R0 R/W R0 R/W R0 Initial value 0 0 0 0 0 This register sets the Low Pass Filter Coefficient. It specifies independently in 2-bit coefficient code with a luminance signal (Y) and a color-difference signal (C). A coefficient is a right-and-left symmetrical coefficient. A Vertical low path filter consists of FIR filters of three taps. A coefficient is specified in the following register. Bit 27 to 26 CVLPF_Y (Capture Vertical LPF coefficient Y) Sets Y part of vertical LPF coefficient code CVLPF_Y 2'b00 2'b01 2'b10 2'b11 Bit 25 to 24 K0 0 1/4 3/16 Reserve K1 1 2/4 10/16 K2 0 1/4 3/16 CVLPF_C (Capture Vertical LPF coefficient C) Sets C part of vertical LPF coefficient code CVLPF_C 2'b00 2'b01 2'b10 2'b11 K0 0 1/4 3/16 Reserve K1 1 2/4 10/16 K2 0 1/4 3/16 A horizontal low path filter consists of FIR filters of five taps. A coefficient is specified in the following register. Bit 19 to 18 CHLPF_YI (Capture Horizontal LPF coefficient Y) Sets Y part of horizontal coefficient code CHLPF_Y 2'b00 2'b01 2'b10 2'b11 Bit 17 to 16 K0 0 0 0 3/32 K1 0 1/4 3/16 8/32 K2 1 2/4 10/16 10/32 K3 0 1/4 3/16 10/32 K4 0 0 0 3/32 CHLPF_C (Capture Horizontal LPF coefficient C) Sets C part of horizontal coefficient code CHLPF_C 2'b00 2'b01 2'b10 2'b11 K0 0 0 0 3/32 K1 0 1/4 3/16 8/32 K2 1 2/4 10/16 10/32 K3 0 1/4 3/16 10/32 K4 0 0 0 3/32 LPF will be turned off if coefficient code 2'b00 are set up. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 214 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CDCN (Capture Data Count for NTSC) Register CaputureBaseAddress + 4000H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved BDCN Reserved VDCN R/W RX RW RX RW Initial value X 10f H (271D) X 5A3H (1443) This register sets the count of data of the input video stream in NTSC format. Bit 25 to 16 BDCN (Blanking Data Count for NTSC) Sets count of data processed during blanking period in NTSC format Bit 10 to 0 VDCN (Valid Data Count for NTSC) Sets count of data processed during valid period in NTSC format CDCP (Capture Data Count for PAL) Register CaputureBaseAddress + 4004H address Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved BDCP Reserved VDCP R/W RX RW RX RW Initial value X 11BH (283D) X 5A3H (1443) This register sets the count of data of the input video stream in PAL format. Bit 25 to 16 BDCP (Blanking Data Count for PAL) Sets count of data processed during blanking period in PAL format Bit 10 to 0 VDCP (Valid Data Count for PAL) Sets count of data processed during valid period in PAL format MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 215 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.5 Drawing control registers CTR (Control Register) Register DrawBaseAddress + 400H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FO CE FCNT NF FF FE SS DS PS R/W RW RW RW R RRR R R R Initial value 000 011101 001 00 00 00 This register indicates drawing flags and status information. Bits 24 to 22 are not cleared until 0 is set. Bit 1 and 0 PS (Pixel engine Status) Indicate status of pixel engine unit 00 01 10 11 Idle Busy Reserved Reserved Bit 5 and 4 DS (DDA Status) Indicate status of DDA 00 01 10 11 Idle Busy Busy Reserved Bit 9 and 8 SS (Setup Status) Indicate status of Setup unit 00 01 10 11 Idle Busy Reserved Reserved Bit 12 FE (FIFO Empty) Indicates whether data contained or not in display list FIFO 0 1 Valid data No valid data Bit 13 FF (FIFO Full) Indicates whether display list FIFO is full or not 0 1 Not full Full Bit 14 NF (FIFO Near Full) Indicates how empty the display list FIFO is MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 216 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 0 1 Empty entries equal to or more than half Empty entries less than half Bit 20 to 15 FCNT (FIFO Counter) Indicates count of empty entries of display list FIFO (0 to 100000b) Bit 23-22 CE (Display List Command Error) Indicates command error occurrence 00 11 Normal Command error detected Bit 24 FO (FIFO Overflow) Indicates FIFO overflow occurrence 0 1 Normal FIFO overflow detected MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 217 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL IFSR (Input FIFO Status Register) Register DrawBaseAddress + 404H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name NF FF FE R/W RRR Initial value 001 This is a mirror register for bits 14 to 12 of the CTR register. IFCNT (Input FIFO Counter) Register DrawBaseAddress + 408H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FCNT R/W R Initial value 011101 This is a mirror register for bits 19 to 15 of the CTR register. SST (Setup engine Status) Register DrawBaseAddress + 40CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name SS R/W R Initial value 00 This is a miller register for bits 9 to 8 of the CTR register. DST (DDA Status) Register DrawBaseAddress + 410H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name DS R/W RW Initial value 00 This is a mirror register for bits 5 to 4 of the CTR register. PST (Pixel engine Status) Register DrawBaseAddress + 414H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name PS R/W R Initial value 00 This is a mirror register for bits 1 to 0 of the CTR register. EST (Error Status) Register DrawBaseAddress + 418H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FO PE CE R/W RW RW RW Initial value 000 This is a mirror register for bits 24 to 22 of the CTR register. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 218 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.6 Drawing mode registers When write to the registers, use the SetRegister command. The registers cannot be accessed from the CPU. MDR0 (Mode Register for miscellaneous) Register DrawBaseAddress + 420H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ZP CF CY CX BSV BSH R/W RW RW RW RW RW RW Initial value 0 00 00 00 00 Bit 1 to 0 BSH (Bitmap Scale Horizontal) Sets horizontal zoom ratio of bitmap draw 00 01 10 01 Bit 3 to 2 x1 x2 x1/2 Reserved BSV (Bitmap Scale Vertical) Sets vertical zoom ratio of bitmap draw 00 01 10 01 x1 x2 x1/2 Reserved Bit 8 CX (Clip X enable) Sets X coordinates clipping mode 0 1 Disabled Enabled Bit 9 CY (Clip Y enable) Sets Y coordinates clipping mode 0 1 Disabled Enabled Bit 16 and 15 CF (Color Format) Sets drawing color format 00 01 Indirect color mode (8 bits/pixel) Direct color mode (16 bits/pixel) Bit 20 ZP (Z Precision) Sets the precision of the Z value used for erasing hidden planes. 16 bits/pixel 8 bits/pixel MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 219 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL MDR1/MDR1S/MDR1B (Mode Register for LINE/for Shadow/for Border) Register DrawBaseAddress + 424H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Bit field name LW BP BL R/W RW RW RW Initial value 00000 00 11 10 9 8 7 6 5 4 3 2 1 0 LOG BM ZW ZCL ZC RW RW RW RW RW 0011 0 0 0000 0 This register sets the mode of line and pixel drawing. This register is used for the body primitive, for the shade primitive, for the edge primitive. The value after a drawing that involves the shade primitive, the edge primitive is the value set for MDR1. The ZC bit of MDR1 is also used for point drawing. But in case of DrawPixelZ command, this bit automatically set to 1. Please set ZC bit ( bit 2) to 0 when draw BltCopyAltAlphaBlendP command. Bit 1 AS (Alpha Shading mode) Sets the shading mode for alpha. 0 1 Alpha flat shading Alpha Gouraud shading Bit 2 ZC (Z Compare mode) Sets Z comparison mode 0 1 Disabled Enabled Bit 5 to 3 ZCL (Z Compare Logic) Selects type of Z comparison 000 001 010 011 100 101 110 111 NEVER ALWAYS LESS LEQUAL EQUAL GEQUAL GREATER NOTEQUAL Bit 6 ZW (Z Write mode) Sets Z write mode 0 1 Writes Z values. Not write Z values. Bit 8 to 7 BM (Blend Mode) Sets blend mode 00 01 Normal (source copy) Alpha blending MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 220 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 10 11 Drawing with logic operation Reserved Bit 12 to 9 LOG (Logical operation) Sets type of logic operation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLEAR AND AND REVERSE COPY AND INVERTED NOP XOR OR NOR EQUIV INVERT OR REVERSE COPY INVERTED OR INVERTED NAND SET Bit 19 BL (Broken Line) Selects line type 0 1 Solid line Broken line Bit 20 BP (Broken line Period) Selects broken line cycle 0: 1: 32 bits 24 bits Bit 28 to 24 LW (Line Width) Sets line width for drawing line 00000 00001 : 11111 1 pixel 2 pixels : 32 pixels MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 221 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL MDR2/MDR2S/MDR2TL (Mode Register for Polygon/for Shadow/for TopLeft) Register DrawBaseAddress + 428H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Bit field name TT R/W RW Initial value 00 11 10 9 8 7 6 5 4 3 2 1 0 LOG BM ZW ZCL ZC AS SM RW RW RW RW RW RW RW 0011 0 0 0000 0 0 0 This register sets the polygon drawing mode. This register is used for the body primitive, for the shade primitive, and for the top-left non-applicable primitive. The value after a drawing that involves the shade primitive or the top-left non-applicable primitive is the value set for MDR2. MDR2S register is able to use only SM=0, AS=0 and TT=00 settings. Bit 0 SM (Shading Mode) Sets shading mode 0 1 Flat shading Gouraud shading Bit 1 AS (Alpha Shading mode) Sets alpha shading mode. This mode is enabled for only alpha. 0 1 Alpha flat shading Alpha gouraud shading Bit 2 ZC (Z Compare mode) Sets Z comparison mode 0 1 Disabled Enabled Bit 5 to 3 ZCL (Z Compare Logic) Selects type of Z comparison 000 001 010 011 100 101 110 111 NEVER ALWAYS LESS LEQUAL EQUAL GEQUAL GREATER NOTEQUAL Bit 6 ZW (Z Write mask) Sets Z write mode 0 1 Writes Z values Not write Z values MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 222 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Bit 8 to 7 BM (Blend Mode) Sets blend mode 00 01 10 11 Normal (source copy) Alpha blending Drawing with logic operation Reserved Bit 12 to 9 LOG (Logical operation) Sets type of logic operation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLEAR AND AND REVERSE COPY AND INVERTED NOP XOR OR NOR EQUIV INVERT OR REVERSE COPY INVERTED OR INVERTED NAND SET Bit 29 to 28 TT (Texture-Tile Select) Selects texture or tile pattern 00 01 10 11 Neither used Enabled tiling Enabled texture Reserved MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 223 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL MDR3 (Mode Register for Texture) Register DrawBaseAddress + 42CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BA TAB TBL TWS TWT TF TC R/W RW RW RW RW RW RW RW Initial value 0 00 00 00 00 0 0 This register sets the texture mapping mode. Bit 3 TC (Texture coordinates Correct) Sets texture coordinates correction mode 0 1 Disabled Enabled Bit 5 TF (Texture Filtering) Sets type of texture interpolation (filtering) 0 1 Point sampling Bi-linear filtering Bit 9 and 8 TWT (Texture Wrap T) Sets type of texture coordinates T direction wrapping 00 01 10 11 Repeat Cramp Border Reserved Bit 11 and 10 TWS (Texture Wrap S) Sets type of texture coordinates S direction wrapping 00 01 10 11 Repeat Cramp Border Reserved Bit 17 and 16 TBL (Texture Blend mode) Sets texture blending mode 00 01 10 11 De-curl Modulate Stencil Reserved Bit 21 and 20 TAB (Texture Alpha Blend mode) Sets texture blending mode The stencil mode and the stencil alpha mode are enabled only when the MDR2 register blend mode (BM) is set to the alpha blending mode. If it is not set to the alpha blending mode, the stencil mode and stencil alpha mode perform the same function as the normal mode. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 224 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 00 01 10 11 Normal Stencil Stencil alpha Reserved Bit 24 BA (Bilinear Accelerate Mode) Improves the performance of bi-linear filtering, although a texture area of four times the default texture area is used. 0 1 Default texture area used Texture area four times default texture area used MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 225 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL MDR4 (Mode Register for BLT) Register DrawBaseAddress + 430H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name LOG BM TE R/W RW RW RW Initial value 0011 00 0 This register controls the BLT mode. Bit 1 TE (Transparent Enable) Sets transparent mode 0: 1: Not perform transparent processing Not draw pixels that corresponds to set transparent color in BLT (transparancy copy) Note: Set the blend mode (BM) to normal. Bit 8 to 7 BM (Blend Mode) Sets blend mode 00 01 10 11 Normal (source copy) Reserved Drawing with logic operation Reserved Bit 12 to 9 LOG (Logical operation) Sets logic operation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLEAR AND AND REVERSE COPY AND INVERTED NOP XOR OR NOR EQUIV INVERT OR REVERSE COPY INVERTED OR INVERTED NAND SET MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 226 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL MDR7 (Mode Register for Extension) Register DrawBaseAddress + 43CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name LTH EZ GG PGH PTHPZH R/W WWW WWW Initial value 100 0 00 This register controls the BLT mode. Bit 0 PZH (Polygon Z Hard mask) Sets polygon-fill Z reference mode 0: 1: Hard mask on ( compatible Orchid) Hard mask off ( extension mode) Bit 1 PTH (Polygon Texture Hard mask) Sets polygon-texture mode 0: 1: Hard mask on ( compatible Orchid) Hard mask off ( extension mode) Bit 2 PGH (Polygon Gouraud shading Hard mask) Sets polygon-gouraud shading mode 0: 1: Hard mask o n ( compatible Orchid) Hard mask off ( extension mode) Bit 4 GG (Gray scale Gouraud Shading) Sets gray scale gouraud shading mode 0: 1: Hard mask on ( compatible Orchid) Hard mask off ( extension mode) Bit 5 EZ (Extend Z) Sets new Z mode 0: 1: Z 1 bit extend off ( compatible Orchid) Z 1 bit extend on ( extension mode) Bit 6 LTH (Line Texture Hard mask) Sets line texture mode 0: 1: Hard mask on ( compatible Orchid) Hard mask off ( extension mode) Note: This register is used for gray scale gouraud shading. This register is changed by internal processing. Please don't set these bits except GG bit. In case of gray scale gouraud shading drawing, please set this register to the follows. 1. Set this register to 0x00000050( GG bit and LTH bit equal to 1) before drawing. 2. Set this register to 0x00000040( LTH bit equal to 1) after drawing. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 227 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL FBR (Frame buffer Base) Register DrawBaseAddress + 440H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FBASE R/W RW R0 Initial value Don't care 0 This register stores the base address of the drawing frame. XRES (X Resolution) Register DrawBaseAddress + 444H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name XRES R/W RW Initial value Don't care This register sets the drawing frame horizontal resolution. ZBR (Z buffer Base) Register DrawBaseAddress + 448H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ZBASE R/W RW R0 Initial value Don't care 0 This register sets the Z buffer base address. TBR (Texture memory Base) Register DrawBaseAddress + 44CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name TBASE R/W RW R0 Initial value Don't care 0 This register sets the texture memory base address. PFBR (2D Polygon Flag-Buffer Base) Register address Bit number Bit field name R/W Initial value DrawBaseAddress + 450H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFBASE RW Don't care R0 0 This register sets the polygon flag buffer base address. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 228 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL CXMIN (Clip X minimum) Register DrawBaseAddress + 454H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CLIPXMIN R/W RW Initial value Don't care This register sets the clip frame minimum X position. CXMAX (Clip X maximum) Register DrawBaseAddress + 458H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CLIPXMAX R/W RW Initial value Don't care This register sets the clip frame maximum X position. CYMIN (Clip Y minimum) Register DrawBaseAddress + 45CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CLIPYMIN R/W RW Initial value Don't care This register sets the clip frame minimum Y position. CYMAX (Clip Y maximum) Register DrawBaseAddress + 460H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CLIPYMAX R/W RW Initial value Don't care This register sets the clip frame maximum Y position. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 229 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL TXS (Texture Size) Register DrawBaseAddress + 464H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name TXSN TXSM R/W RW RW Initial value 000010000000 000010000000 This register specifies the texture size (m, n). Bit 12 to 0 TXSM (Texture Size M) Sets horizontal texture size. Any power of 2 between 4 and 4096 can be used. Values that are not a power of 2 cannot be used. 0_0000_0000_0100 0_0000_0000_1000 0_0000_0001_0000 0_0000_0010_0000 0_0000_0100_0000 0_0000_1000_0000 0_0001_0000_0000 M=4 M=8 M=16 M=32 M=64 M=128 M=256 Other than the above Setting disabled 0_0010_0000_0000 0_0100_0000_0000 0_1000_0000_0000 1_0000_0000_0000 M=512 M=1024 M=2048 M=4096 Bit 28 to 16 TXSN (Texture Size N) Sets vertical texture size. Any power of 2 between 4 and 4096 can be used. Values that are not a power of 2 cannot be used. 0_0000_0000_0100 0_0000_0000_1000 0_0000_0001_0000 0_0000_0010_0000 0_0000_0100_0000 0_0000_1000_0000 0_0001_0000_0000 N=4 N=8 N=16 N=32 N=64 N=128 N=256 Other than the above Setting disabled 0_0010_0000_0000 0_0100_0000_0000 0_1000_0000_0000 1_0000_0000_0000 N=512 N=1024 N=2048 N=4096 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 230 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL TIS (Tile Size) Register DrawBaseAddress + 468H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name TISN TISM R/W RW RW Initial value 1000000 1000000 This register specifies the tile size (m, n). Bit 6 to 0 TISM (Title Size M) Sets horizontal tile size. Any power of 2 between 4 and 64 can be used. Values that are not a power of 2 cannot be used. 0.000100 0001000 0010000 0100000 1000000 Other than the above M=4 M=8 M=16 M=32 M=64 Setting disabled Bit 22 to 16 TISN (Title Size N) Sets vertical tile size. Any power of 2 between 4 and 64 can be used. Values that are not a power of 2 cannot be used. 0000100 0001000 0010000 0100000 1000000 Other than the above N=4 N=8 N=16 N=32 N=64 Setting disabled TOA (Tiling Offset address) Register DrawBaseAddress + 46CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name XBO R/W RW Initial value Don't care This register sets the texture buffer offset address. Using this offset value, texture patterns can be referred to the texture buffer memory. TOA is used for only the tiling drawing, and is n used for ot referring the texture pattern. Specify the word-aligned byte address (16 bits). (Bit 0 is always "0".) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 231 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL SHO (SHadow Offset) Register DrawBaseAddress + 470H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name SHOFFS R/W RW Initial value Don't care This register sets the offset address of the shadow relative to the body primitive at drawing with shadow. At body drawing, this offset address is set to "0"; at shadow drawing, the offset address calculated from each offset value of the X coordinates and of the Y coordinates is set. This register is hardware controlled. ABR (Alpha map Base) Register DrawBaseAddress + 474H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ABASE R/W RW R0 Initial value Don't care 0 This register sets the base address of the alpha map. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 232 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL FC (Foreground Color) Register DrawBaseAddress + 480H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FGC8/16 R/W RW Initial value 0 This register sets the drawing foreground color. This color is for the object color for flat shading and foreground color for bitmap drawing and broken line drawing. All bits set to "1" are drawn in the color set at this register. 8 bit color mode: Bit 7 to 0 FGC8 (Foreground 8 bit Color) Sets the indirect color for the foreground (color index code). Bit 31 to 8 These bits are not used. 16 bit color mode: Bit 15 to 0 FGC16 (Foreground 16 bit Color) This field sets the 16-bit direct color for the foreground. Note that the handling of bit 15 is different from that in ORCHID. Up to ORCHID, bit 15 is "0" for other than bit map and rectangular drawing, but starting with CORAL, the setting value is reflected in memory as is. This bit is also reflected in bit 15 of the 16-bit color at Gouraud shading. Bit 31 to 16 These bits are not used. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 233 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL BC (Background Color) Register DrawBaseAddress + 484H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BGC8/16 R/W RW Initial value 0 This register sets the drawing frame background color. This color is used for the background color of bitmap drawing and broken line drawing. At bitmap drawing, all bits set to "0" are drawn in the color set at this register. BT bit of this register allows the background color of be transparent (no drawing). 8 bit color mode: Bit 7 to 0 BGC8 (Background 8 bit Color) Sets the indirect color for the background (color index code) Bit 14 to 8 Bit 15 Not used BT (Background Transparency) Sets the transparent mode for the background color 0 1 Bit 31 to 16 Background drawn using color set for BGC field Background not drawn (transparent) Not used 16 bit color mode: Bit 14 to 0 BGC16 (Background 16 bit Color) Sets 16-bit direct color (RGB) for the background Bit 15 BT (Background Transparency) Sets the transparent mode for the background color 0 1 Bit 31 to 16 Background drawn using color set for BGC field Background not drawn (transparent) Not used MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 234 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL ALF (Alpha Factor) Register DrawBaseAddress + 488H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R/W RW Initial value 0 This register sets the alpha blending coefficient. BLP (Broken Line Pattern) Register DrawBaseAddress + 48CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BLP R/W RW Initial value 0 This register sets the broken-line pattern. The bit 1 set in the broken-line pattern is drawn in the foreground color and bit 0 is drawn in the background color. The line pattern for 1 pixel line is laid out in the direction of MSB to LSB and when it reaches LSB, it goes back to MSB. The BLPO register manages the bit numbers of the broken-line pattern. 32 or 24 bits can be selected as the repetition of the broken-line pattern by the BP bit of the MDR1 register. When 24 bits are selected, bits 23 to 0 of the BLP register are used. TBC (Texture Border Color) Register DrawBaseAddress + 494H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BC8/16 R/W RW Initial value 0 This register sets the border color for texture mapping. 8 bit color mode: Bit 7 to 0 BC8 (Border Color) Sets the 8-bit direct color for the texture border color 16 bit color mode: Bit 15 to 0 BC16 (Border Color) Sets the 16-bit direct color for the texture border color Bit15 is used for controlling a stencil and stencil alpha BLPO (Broken Line Pattern Offset) Register DrawBaseAddress + 3E0H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BCR R/W RW Initial value 11111 This register stores the bit number of the broken-line pattern set to BLP registers, for broken line drawing. This value is decremented at each pixel drawing. Broken line can be drawn starting from any starting position of the specified broken-line pattern by setting any value at this register. When no write is performed, the position of broken-line pattern is sustained. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 235 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 236 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL PNBPI (Pixel Number of Broken line pattern Pointer Inter lock) Register DrawBaseAddress + 28CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name PN R/W W Initial value 00000 This register is valid when BC(16bit)=1 of the GMDR1E register, and determines how many pixels should be fixed before and behind reference address of broken-line pattern(broken-line pointer). The recommended value is same as the line width. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 237 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.7 Triangle drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. (XY coordinates register) Register Address Ys Xs dXdy XUs dXUdy XLs dXLdy USN LSN 0000H 0004H 0008H 000cH 0010H 0014H 0018H 001cH 0020H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S SS S Int Frac S SS S Int Frac S SS S Int Frac S SS S Int Frac S SS S Int Frac S SS S Int Frac S SS S Int Frac 0000 Int 0 0000 Int 0 Address S 0 Int Frac Offset value from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets (X, Y) coordinates for triangle drawing Ys Xs dXdy XUs dXUdy XLs dXLdy USN LSN Y coordinates start position of long edge X coordinates start position of long edge corresponding to Ys X DDA value of long edge direction X coordinates start position of upper edge X DDA value of upper edge direction X coordinates start position of lower edge X DDA value of lower edge direction Count of spans of upper triangle. If this value is "0", the upper triangle is not drawn. Count of spans of lower triangle. If this value is "0", the lower triangle is not drawn. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 238 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL (Color setting register) Register Address 31 Rs dRdx dRdy Gs dGdx dGdy Bs dBdx dBdy 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005cH 0060H 0 S S 0 S S 0 S S 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000 Int Frac SS S SS SS Int Frac SS S SS SS Int Frac 0000000 Int Frac SS S SS SS Int Frac SS S SS SS Int Frac 0000000 Int Frac SS S SS SS Int Frac SS S SS SS Int Frac Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets color parameters for triangle drawing. These parameters are enabled in the Gouraud shading mode. Rs dRdx dRdy Gs dGdx dGdy Bs dBdx dBdy R value at (Xs, Ys, Zs) of long edge corresponding to Ys R DDA value of horizontal direction R DDA value of long edge G value at (Xs, Ys, Zs) of long edge corresponding to Ys G DDA value of horizontal direction G DDA value of long edge B value at (Xs, Ys, Zs) of long edge corresponding to Ys B DDA value of horizontal direction B DDA value of long edge (Z coordinates register) Register Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Zs 0080h 0 Int Frac dZdx 0084h S Int Frac dZdy 0088h S Int Frac Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets Z coordinates for 3D triangle drawing Zs dZdx dZdy Z coordinate start position of long edge Z DDA value of horizontal direction Z DDA value of long edge MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 239 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL (Texture coordinates-setting register) Register Address Ss dSdx dSdy Ts dTdx dTdy Qs dQdx dQdy 00c0H 00c4H 00c8H 00ccH 00d0H 00d4H 00d8H 00dcH 00e0H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S SS Int Frac S SS Int Frac S SS Int Frac S SS Int Frac S SS Int Frac S SS Int Frac 0 0 0 0 0 0 0 Int Frac S S S S S S S Int Frac S S S S S S S Int Frac Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets texture coordinates parameters for triangle drawing Ss dSdx dSdy Ts dTdx dTdy Qs dQdx dQdy S texture coordinates (Xs, Ys, Zs) of long edge corresponding to Ys S DDA value of horizontal direction S DDA value of long edge direction T texture coordinates (Xs, Ys, Zs) of long edge corresponding to Ys T DDA value of horizontal direction T DDA value of long edge direction Q (Perspective correction value) of texture at (Xs, Ys, Zs) of long edge corresponding to Ys Q DDA value of horizontal direction Q DDA value of long edge direction MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 240 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.8 Line drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command. (Coordinates setting register) Register Address LPN LXs LXde LYs LYde LZs LZde 0140H 0144H 0148H 014cH 0150H 0154H 0158H 31 0 S S S S S S 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 Int 0 SS S Int Frac S S S S S S S S S S S S S S Int Frac SS S Int Frac S S S S S S S S S S S S S S Int Frac Int Frac Int Frac Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates parameters for line drawing LPN LXs Pixel count of principal axis direction X coordinates start position of draw line (In principal axis X) Integer value of X coordinates rounded off (In principal axis Y) X coordinates in form of fixed point data Inclination data for X coordinates (In principal axis X) Increment or decrement according to drawing direction (In principal axis Y) Fraction part of DX/DY Y coordinates start position of draw line (In principal axis X) Y coordinates in form of fixed point data (In principal axis Y) Integer value of Y coordinates rounded off Inclination data for Y coordinates (In principal axis X) Fraction part of DY/DX (In principal axis Y) Increment or decrement according to drawing direction Z coordinates start position of line drawing line Z Inclination LXde LYs LYde LZs LZde MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 241 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.9 Pixel drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. Register Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PXdc 0180H 0 0 0 0 Int 0 PYdc 0184H 0 0 0 0 Int 0 PZdc 0188H 0 0 0 0 Int 0 Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates parameter for drawing pixel. The foreground color is used. PXdc PYdc PZdc Sets X coordinates position Sets Y coordinates position Sets Z coordinates position 11.2.10 Rectangle drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. Register Address RXs 0200H RYs 0204H RsizeX 0208H RsizeY 020cH 31 0 0 0 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 Int 0 000 Int 0 000 Int 0 000 Int 0 Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates parameters for rectangle drawing. The foreground color is used. RXs RYs RsizeX RsizeY Sets Sets Sets Sets the X coordinates of top left vertex the Y coordinates of top left vertex horizontal size vertical size MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 242 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.11 Blt registers Sets the parameters of each register as described below: * Set the Tcolor register with the SetRegister command. Note that the Tcolor register cannot be set at access from the CPU and by drawing commands. * Each register except the Tcolor register is set by executing a drawing command. Note that access from the CPU and the SetRegister command cannot be used. Register Address SADDR 0240H SStride 0244H SRXs 0248H SRYs 024cH DADDR 0250H DStride 0254 H DRXs 0258H DRYs 025cH BRsizeX 0260 H BRsizeY 0264 H TColor 0280 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000 Address 0000 Int 0 0000 Int 0 0000 Int 0 0000000 Address 0000 Int 0 0000 Int 0 0000 Int 0 0000 Int 0 0000 Int 0 0 Color Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets parameters for Blt operations SADDR SStride SRXs SRYs DADDR DStride DRXs DRYs BRsizeX BRsizeY Tcolor Sets start address of source rectangle area in byte address Sets stride of source Sets X coordinates start position of source rectangle area Sets Y coordinates start position of source rectangle area Sets start address of destination rectangle area in byte address Sets stride of destination Sets X coordinates start position of destination rectangle area Sets Y coordinates start position of destination rectangle area Sets horizontal size of rectangle Sets vertical size of rectangle Sets transparent color For indirect color, set a palette code in the lower 8 bits. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 243 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.12 High-speed 2D line drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU. 31 0 0 0 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 Int 0 000 Int 0 000 Int 0 000 Int 0 Register Address LX0dc LY0dc LX1dc LY1dc 0540H 0544H 0548H 054cH Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates of line end points for High-speed 2DLine drawing LX0dc LY0dc LX1dc LY1dc Sets X coordinates of vertex V0 Sets Y coordinates of vertex V0 Sets X coordinates of vertex V1 Sets Y coordinates of vertex V1 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 244 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.13 High-speed 2D triangle drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. Register Address X0dc Y0dc X1dc Y1dc X2dc Y2dc 0580h 0584h 0588h 058ch 0590h 0594h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 Int 0 0000 Int 0 0000 Int 0 0000 Int 0 0000 Int 0 0000 Int 0 Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates of three vertices for High-speed 2DTriangle drawing X0dc Y0dc X1dc Y1dc X2dc Y2dc Sets X coordinates of vertex V0 Sets Y coordinates of vertex V0 Sets X coordinates of vertex V1 Sets Y coordinates of vertex V1 Sets X coordinates of vertex V2 Sets Y coordinates of vertex V2 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 245 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.14 Geometry control register GCTR (Geometry Control Register) Register GeometryBaseAddress + 00H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved FO Rsv FCNT NF FF FE Rsv GS Rsv SS Rsv PS R/W RX RX RX RX RXRX RX RX R RX R RX R Initial value X 0 X 011111 00 1 X 00 X 00 X 00 The flags and status information of the geometry section are reflected in this register. Note that the flags and status information of the drawing section are reflected in CTR. Bit 1 and 0 PS (Pixel engine Status) Indicates status of pixel engine unit 00 01 10 11 Idle Processing Reserved Reserved Bit 5 and 4 SS (geometry Setup engine Status) Indicates status of geometry setup engine unit 00 01 10 11 Idle Processing Processing Reserved Bit 9 and 8 GS (Geometry engine Status) Indicates status of geometry engine unit 00 01 10 11 Idle Processing Reserved Reserved Bit 12 FE (FIFO Empty) Indicates whether the data is contained in display list FIFO (DFIFOD) 0 1 Data in DFIFOD No data in DFIFOD Bit 13 FF (FIFO Full) Indicates whether display list FIFO (DFIFOD) is full or not 0 1 DFIFOD not full DFIFOD full MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 246 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Bit 14 NF (FIFO Near Full) Indicates free space in display list FIFO (DFIFOD) 0 1 More than half of DFIFOD free Less than half of DFIFOD free Bit 20 to 15 FCNT (FIFO Counter) Indicates count of free stages (0 to 100000B) of display list FIFO (DFIFOD) Bit 24 FO (FIFO Overflow) Indicates whether FIFO overflow occurred 0 1 Normal FIFO overflow MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 247 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.15 Geometry mode registers The SetRegister command is used to write values to geometry mode registers. The geometry mode registers cannot be accessed from the CPU. GMDR0 (Geometry Mode Register for Vertex) Register GeometryBaseAddress + 40H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Bit field name CF R/W RW Initial value 0 6543210 DF ST Z C F RW RW RW RW RW 00 0000 This register sets the types of parameters input as vertex data and the type of projective transformation. Bit 7 CF (Color Format) Specifies color data format 0 1 Independent RGB format / Packed RGB format Reserved Bit 6 and 5 DF (Data Format) Specifies vertex coordinates data format 00 01 10 11 Specifies floating-point format (Only independent RGB format can be used as color data format.) Specifies fixed-point format (Only packed RGB format can be used as color data format.) Reserved Specifies packed integer format (Only packed RGB format can be used as color data format.) CF 0 DF 00 01 10 11 Input data format Floating-point format + independent RGB format Fixed-point format + packed RGB format Reserved Packed integer format + packed RGB format Reserved Reserved Reserved Reserved 1 00 01 10 11 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 248 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Bit 3 ST (texture S and T data enable) Sets whether to use texture ST coordinates 0 1 Not use texture ST coordinates Uses texture ST coordinates Bit 2 Z (Z data enable) Sets whether to use Z coordinates 0 1 Not use Z coordinates Uses Z coordinate s Bit 1 C (Color data enable) Sets whether to use vertex color 0 1 Not use vertex color Uses vertex color Bit 0 F (Frustum mode) Sets projective transformation mode 0 1 Orthogonal projection transformation mode Perspective projection transformation mode MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 249 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL GMDR1 (Geometry Mode Register for Line) Register GeometryBaseAddress + 44H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BO EP AA R/W W W W Initial value 0 0 0 This register sets the geometry mode at line drawing. This register is sharing hardware with GMDR1E, so that if GMDR1 is changed, the same bit of GMDR1E is also changed. Bit 4 BO (Broken line Offset) Sets broken line reference position 0 1 Broken line reference position not cleared Broken line reference position cleared Bit 2 EP (End Point mode) Sets end point drawing mode Note that the end point is not drawn in line strip. 0 1 End point not drawn End point drawn Bit 0 AA (Anti-alias mode) Sets anti-alias mode 0 1 Anti-alias not performed Anti-alias performed MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 250 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL GMDR1E (Geometry Mode Register for Line Extension) Register address (SetGModeRegister) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name P0 TC BC UW BM TM BP SP BO EP AA R/W W W W WWW WW W W W Initial value 0 0 0 000 00 0 0 0 This register sets the geometry processing extended mode at line drawing. The CORAL extended function can be used only when the C, Z, and ST fields of GMDR0 are "0". This register is sharing hardware with GMDR1, so that if GMDR1E is changed, the same bit of GMDR1 is also changed. Bit31 P0 (Primitive Order control) Sets the drawing control mode for the main, the border, and the shadow primitive. Recommend to set main bit=1 in anti -aliasing and blending. 0 Draws the order of, main->border->shadow(performance is regarded as important) Draws the order of , shadow->border->main(blending affect is regarded as important) 1 Bit30 LV (Line Version control) Specify the Coral line's algorithm version. V2.0 is improvement version from V1.0. Recommend V2.0. 0 1 Version 1.0 ( for backward compatibility ) Version 2.0 (Recommended) Bit 20 TC (Thick line Correct) Sets the interpolation mode for the bold line joint 0 Interpolation of bold lien joint not performed Interpolation of bold line joint performed (valid for only CORAL line) 1 Bit 16 BC (Broken line Correct) Sets the interpolation mode for the dashed-line pattern 0 Interpolation not performed 1 Interpolation performed using dashed-line pattern reference address fixed mode (valid for only CORAL line) Bit 14 UW (Uniform line Width) Sets the line width equalization mode 0 1 Equalization of line width not performed Equalization of lien width performed (valid for only CORAL line) Bit 13 BM (Broken line Mode) Sets the dashed-line pattern mode 0 Dashed-line pattern pasted vertical to principal axis of line (compatible with CREMSON) (valid for only CREMSON line) 1 Dashed-line pattern pasted vertical to theoretical line Bit 12 TM (Thick line Mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 251 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Sets the bold line mode 0 Bold line drawn vertical to principal axis of line (compatible with CREMSON) (CREMSON line) Operation is not assured when TM=0 is used together with TC -1, SP=1, or BP=1. 1 Bold line drawn vertical to theoretical line. (CORAL line) Operation is not assured when TM=1 is used together with BM=0. Bit 9 BP (Border Primitive) Sets the drawing mode for the border primitive 0 1 Border primitive not drawn Border primitive drawn (valid for only CORAL line) Bit 8 SP (Shadow Primitive) Sets the drawing mode for the shadow primitive 0 Shadow primitive not drawn Shadow primitive drawn (valid for only CORAL line) 1 Bit 4 BO (Broken line Offset) Sets the reference position of the dashed-line pattern 0 Reference position of dashed-line pattern cleared Reference position of dashed-line pattern not cleared 1 Bit 2 EP (End Point mode) Sets the drawing mode for the end point Note that the end point is always not drawn in line strip(CREMSON line(TN=0)) 0 End point not drawn 1 End point drawn Bit 0 AA (Anti-alias mode) Sets anti-alias mode 0 Anti-alias not performed 1 Anti-alias performed GMDR2 (Geometry Mode Register for Triangle) Register address GeometryBaseAddress + 48H Bit number Bit field name R/W Initial value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FD CF W 0 W 0 This register sets the geometry processing mode when a triangle is drawn. Drawing performed using commands in range from G_Begin/G_BeginCont to G_End Bit 2 FD (Face Definition) Sets the face definition 0 1 Face defined as state with vertexes arranged clockwise Face defined as state with vertexes arranged counterclockwise MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 252 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Bit 0 CF (Cull Face) Sets the drawing mode of the back 0 1 Back drawn Back not drawn (value disabled for polygons) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 253 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL GMDR2E (Geometry Mode Register for Triangle Extension) Register address (SetGModeRegister) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name TL SP FD CF R/W W W W W Initial value 0 0 0 0 This register sets the geometry processing extended mode at triangle drawing. In case of TL=1 with texture mapping, please set perspective correction. Non-top-left-part's pixel quality is less than body. (using approximate calculation) Bit 10 TL (Top-Left rule mode) Sets the drawing algorithm 0 1 Top-left rule applied (compatible with CREMSON) Top-left rule not applied Bit 8 SP (Shadow Primitive) Sets the drawing mode for the shadow primitive 0 1 Shadow primitive not drawn Shadow primitive drawn Bit 2 FD (Face Definition) Sets the face definition 0 1 Face defined as state with vertexes arranged clockwise Face defined as state with vertexes arranged counterclockwise Bit 0 CF (Cull Face) Sets the drawing mode of the b ack 0 1 Back drawn Back not drawn (value disabled for polygons) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 254 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 11.2.16 Display list FIFO registers DFIFOG (Geometry Displaylist FIFO with Geometry) Register Geometry BaseAddress + 400H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name DFIFOG R/W W Initial value Don't care FIFO registers for Display List transfer MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 255 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12 TIMING DIAGRAM 12.1 Host Interface 12.1.1 CPU read/write timing diagram in SH3 mode (Normally Not Ready Mode) ( MODE[2:0]=000, RDY_MODE=0, BS_MODE=0) T1 BCLKI A[24:2] XCS XBS Tsw1 Thw1 T2 T1 Tsw1 Thw1 Thw2 Thw3 T2 At Read XRD D[31:0] XWE[3:0] D[31:0] XWAIT Hi-Z SoftWait HardWait NotWait Hi-Z Valid Data Valid Data Hi-Z At Write Valid Data IN Hi-Z Valid Data IN Hi-Z SoftWait HardWait HardWait HardWait Not Wait : XWAIT sampling in SH3 mode x: Soft Wait (1 cycle) in SH3 mode T1: Read/write start cycle (XRDY in wait state) Tsw*: Software wait insertion cycle (1 cycle setting) Thw*: Hardware wait insertion cycle (XRDY cancels the wait state after the preparations) T2: Read/write end cycle (XRDY ends in wait state) Fig. 10.1 Read/Write Timing Diagram for SH3 (Normally Not Ready Mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 256 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.2 CPU read/write timing diagram in SH3 mode (Normally Ready Mode) ( MODE[2:0]=000, RDY_MODE=1, BS_MODE=0) T1 BCLKI A[24:2] XCS XBS Tsw1 Tsw2 T2 T1 Tsw1 Tsw2 Thw1 Thw2 T2 At Read XRD D[31:0] XWE[3:0] D[31:0] XWAIT Hi-Z SoftWait SoftWait NotWait Valid Data IN Hi-Z SoftWait SoftWait HardWait HardWait NotWait Valid Data IN Hi-Z Hi-Z Hi-Z Valid Data Valid Data At Write : XWAIT sampling in SH3 mode x : Soft Wait (2 cycles) in SH3 mode T1: Read/write start cycle (XRDY in not wait state) Tsw*: Software wait insertion cycle (2-cycle setting required) Thw*: Hardware wait insertion cycle (In hardware state when the immediate accessing is disabled) T2: Read/write end cycle (XRDY ends in not wait state) Fig. 10.2 Read/Write Timing Diagram for SH3 (Normally Ready Mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 257 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.3 CPU read/write timing diagram in SH4 mode (Normally Not Ready Mode) ( MODE[2:0]=001, RDY_MODE=0, BS_MODE=0) T1 Tsw1 Thw1 T2 T1 Tsw1 Thw1 Thw2 Thw3 T2 BCLKI A[24:2] XCS XBS At Read XRD Hi-Z D[31:0] XWE[3:0] D[31:0] XRDY Hi-Z SoftWaiit HardWait Ready SoftWait HardWait HardWait HardWait Ready Valid Data IN Valid Data IN Hi-Z Valid Data OUT Valid Data OUT At Write : XRDY sampling in SH4 mode x : Soft Wait (1 cycle) in SH4 mode T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (1 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T2: Read/write end cycle (XRDY ends in not ready state) Fig. 10.3 Read/Write Timing Diagram for SH4 Mode (Normally Not Ready Mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 258 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.4 CPU read/write timing diagram in SH4 mode (Normally Ready Mode) ( MODE[2:0]=001, RDY_MODE=1, BS_MODE=0) T1 BCLKI A[24:2] XCS XBS Tsw1 Tsw2 T2 T1 Tsw1 Tsw2 Thw1 Thw2 T2 At Read XRD D[31:0] XWE[3:0] D[31:0] XRDY Hi-Z SoftWaiit SoftWait Ready SoftWait SoftWait HardWait HardWait Ready Valid Data IN Valid Data IN Hi-Z Hi-Z Valid Data OUT Valid Data OUT At Write : XRDY sampling in SH4 mode x : Soft Wait (2 cycles) in SH4 mode T1: Read/write start cycle (XRDY in ready state) Tsw*: Software wait insertion cycle (2-cycle setting required) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T2: Read/write end cycle (XRDY ends in ready state.) Fig. 10.4 CPU Read/Write Timing Diagram for SH4 Mode (Normally Ready Mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 259 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.5 CPU read/write timing diagram in V832 mode (Normally Not Ready Mode) ( MODE[2:0]=010, RDY_MODE=0, BS_MODE=0) T1 BCLKI A[23:2] XCS XB1CYST Tsw1 Thw1 T2 T1 Tsw1 Thw1 Thw2 Thw3 T2 At Read XMRD(XIORD) D[31:0] XMWR(XIOWR) XXXBEN[3:0] D[31:0] XREADY Hi-Z SoftWaiit HardWait Ready SoftWait HardWait HardWait HardWait Ready Valid Data IN Valid Data IN Hi-Z Hi-Z Valid Data OUT Valid Data OUT Hi-Z At Write : XREADY sampling in V832 mode T1: Read/write start cycle (XREADY in not ready state) x: Soft Wait (1 cycle) in V832 mode Tsw*: Software wait insertion cycle Twh*: Hardware wait insertion cycle (XREADY asserts Ready after the preparations) T2: Read/write end cycle (XREADY ends in not ready state) 1.The XxxBEN signal is used only for a write from the CPU; it is not used for a read from the CPU. 2.The CPU always inserts one cycle wait after read access. Notes: Fig. 10.5 Read/Write Timing Diagram in V832 Mode (Normally Not Ready Mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 260 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.6 CPU read/write timing diagram in V832 mode (Normally Ready Mode) ( MODE[2:0]=010, RDY_MODE=1, BS_MODE=0) T1 BCLKI A[23:2] XCS XBCYST Tsw1 Tsw2 T2 T1 Tsw1 Tsw2 Thw1 Thw2 T2 At Read XMRD(XIORD) D[31:0] Hi-Z Valid Data OUT Valid Data OUT Hi-Z At Write XMWR(XIOWR) XXXBEN[3:0]) D[31:0] XREADY Hi-Z SoftWaiit SoftWait Ready SoftWait SoftWait HardWait HardWait Ready Valid Data IN Valid Data IN Hi-Z : XREADY sampling in V832 mode x: Soft Wait (2 cycles) in V832 mode T1: Read/write start cycle (XREADY in ready state) Tsw*: Software wait insertion cycle (2-cycle setting required) Twh*: Hardware wait insertion cycle (XREADY asserts Ready after the preparations) T2: Read/write end cycle (XREADY ends in ready state) 1.The XxxBEN signal is used only for a write from the CPU; it is not used for a read from the CPU. 2.The CPU always inserts one cycle wait after read access. Notes: Fig. 10.6 Read/Write Timing Diagram in V832 Mode (Normally Ready Mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 261 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.7 CPU read/write timing diagram in SPARClite (Normally Not Ready Mode) ( MODE[2:0]=011, RDY_MODE=0, BS_MODE=0) T1 CLKINI ADR[23:2] CS# AS# Tsw1 Thw1 T2 T1 Tsw1 Thw1 Thw2 Thw3 T2 At Read RDWR# D[31:0] RDWR# BE[3:0]# D[31:0] READY# Hi-Z SoftWaiit HardWait Ready Valid Data IN Hi-Z SoftWait HardWait HardWait HardWait Ready Valid Data IN Hi-Z Hi-Z Valid Data Valid Data Hi-Z At Write : READY# sampling in SPARClite x: Soft Wait (1 cycle) in SPARClite T1: Read/write start cycle (READY# in not ready state) Tsw*: Software wait insertion cycle Twh*: Hardware wait insertion cycle (READY# asserts Ready after the preparations) T2: Read/write end cycle (READY# ends in not ready state) Note: BE# signal is used only for a write from the CPU; it is not used for a read from the CPU. Fig. 10.7 Read/Write Timing Diagram in SPARClite (Normally Not Ready Mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 262 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.8 CPU read/write timing diagram in SPARClite (Normally Ready Mode) ( MODE[2:0]=011, RDY_MODE=1, BS_MODE=0) T1 CLKINI ADR[23:2] CS# AS# Tsw1 Tsw1 T2 T1 Tsw1 Tsw1 Thw1 Thw2 T2 At Read RDWR# D[31:0] RDWR# Hi-Z Valid Data Valid Data Hi-Z At Write BE#[3:0] D[31:0] READY# Hi-Z SoftWaiit SoftWait Ready Valid Data IN Hi-Z SoftWait HardWait HardWait HardWait Ready Valid Data IN Hi-Z : READY# sampling in SPARClite x: Soft Wait (1 cycle) in SPARClite T1: Read/write start cycle (READY# in ready state) Tsw*: Software wait insertion cycle (2-cycle setting required) Twh*: Hardware wait insertion cycle (READY# asserts Ready after the preparations) T2: Read/write end cycle (READY# ends in ready state) Note: BE# signal is used only for a write from the CPU; it is not used for a read from the CPU. Fig. 10.8 Read/Write Timing Diagram in SPARClite (Normally Ready Mode) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 263 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.9 SH4 single-address DMA write (transfer of 1 long word) BCLKIN D[31:0] DREQ DRACK DTACK Bus cycle CPU DMAC *1 DMAC CPU *1 Acceptance Acceptance Acceptance : *1: DREQ sampling and channel priority determination for SH mode (DREQ = level detection) In the cycle steal mode, even when DREQ is already asserted at the 2nd DREQ sampling, the right to use the bus is returned to the CPU temporarily. In the burst mode, DMAC secures the right to use the bus unless DREQ is negated. Fig. 10.9 SH4 Single-address DMA Write (Transfer of 1 Long Word) CORAL writes data according to the DTACK assert timing. When data cannot be received, the DREQ signal is automatically negated. And then the DREQ signal is reasserted as soon as data reception is ready. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 264 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.10 SH4 single-address DMA write (transfer of 8 long words) BCLKIN D[31:0] DREQ DRACK DTACK Bus cycle CPU DMAC CPU Acceptance Acceptance : DREQ sampling and channel priority determination for SH mode (DREQ = level detection) Fig. 10.10 SH4 Single-address DMA Write (Transfer of 8 Long Words) After the CPU has asserted DRACK, CORAL negates DREQ and receives 32-byte data in line with the DTACK assertion timing. As soon as the next data is ready to be received, CORAL reasserts DREQ but the reassertion timing depends on the internal status. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 265 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.11 SH3/4 dual-address DMA (transfer of 1 long word) BCLKIN DREQ Source address A[24:2] Read D[31:0] Destination address Source address Destination address Write Read Write For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. 10.11 SH3/4 Dual-address DMA (Transfer of 1 Long Word) In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default. Consequently, when CORAL cannot return the ready signal immediately, in order to negate the DREQ signal set the DBM register. 12.1.12 SH3/4 dual-address DMA (transfer of 8 long words) BCLKIN DREQ Source address A[24:2] Read 1 D[31:0] ......... Read 2 ......... ......... Read 8 Destination address ......... Write 1 Write 2 ......... ......... Write 8 For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. 10.12 SH3/4 Dual-address DMA (Transfer of 8 Long Words) In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default. Consequently, when CORAL cannot return the ready signal immediately, in order to negate the DREQ signal set the DBM register. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 266 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.13 V832 DMA transfer BCLKIN DMARQ DMAAK Source address A[23:2] Read D[31:0] Destination address Source address Destination address Write Read Write For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. 10.13 V832 DMA Transfer In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default. Consequently, when CORAL cannot return the ready signal immediately, in order to negate the DREQ signal set the DBM register. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 267 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.14 SH4 single-address DMA transfer end timing BCLKIN D[31:0] DREQ DRACK DTACK Last data Acceptance Acceptance : DREQ sampling and channel priority determination for SH mode (DREQ = level detection) Fig. 10.14 SH4 Single-address DMA Transfer End Timing DREQ is negated three cycles after DRACK is written as the last data. 12.1.15 SH3/4 dual-address DMA transfer end timing BCLKIN DREQ DRACK Source address A[24:2] Read D[31:0] Write Destination address DTACK For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. 10.15 SH3/4 Dual-address DMA Transfer End Timing DREQ is negated three cycles after DRACK is written as the last data. Note: When the dual address mode (DMA) is used, the DTACK signal is not used. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 268 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.16 V832 DMA transfer end timing BCLKIN DMARQ Source address A[24:2] Read Write Destination address D[31:0] DMAAK XTC For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. 10.16 V832 DMA Transfer End Timing DMMAK and XTC are logic ANDed inside CORAL to end DMA. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 269 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.17 SH4 dual DMA write without ACK 1 CLK 2 3 4 /DREQ When CORAL can not receive data immediately, DREQ negation continues. /BS While DREQ is issued at each write access to CORAL, DREQ is negated at every four cycles.. /RD /WE[3:0] ADDRESS /CS(CORAL) Right to use bus CPU DMAC SAR DAR Fig. 10.17 DREQ Negate Timing for Each Transfer At each DMA transfer, DREQ is negated and then reasserted at the next cycle. Only the FIFO address can be used as the destination address. When CORAL cannot receive data immediately, DREQ negation continues. At that time, the negate timing is not only above diagram. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 270 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.1.18 Dual-address DMA (without ACK) end timing /DREQ Right to use bus CPU DMAC CPU DMAC CPU Fig. 10.18 Dual-address DMA (without ACK) End Timing Example: DMA operation when DMA transfer performed twice (1) The CPU accesses the DREQ issue register (DRQ) of Coral to issue DREQ. (2) The right to use bus is transferred from the CPU to the DMAC. (3) In the first DMAC cycle, write is performed to CORAL and DREQ is negated; DREQ is reasserted in the next cycle. (4) The right to use bus is returned to the CPU and the DREQ edge is detected, so the right to use bus is transferred to the DMAC. (5) The second write operation is performed and DREQ is negated, but DREQ is reasserted because CORAL does not recognize that the transfer has ended. (6) The right to use bus is transferred to the CPU, so the CPU writes to the DTS register of CORAL to negate DREQ. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 271 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.2 Graphics Memory Interface The CORAL access timing and graphics memory access timing are explained here. 12.2.1 Timing of read access to same row address MCLKO MRAS TRCD MCAS MWE MA ROW COL COL COL COL CL MD DATA DATA DATA DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRCD: RAS to CAS Delay Time CL: CAS Latency *Timing when CL2 operating Fig. 10.19 Timing of Read Access to Same Row Address The above timing diagram shows that read access is made four times from CORAL to the same row address of SDRAM. The ACTV command is issued and then the READ command is issued after TRCD elapses. Then data that is output after the elapse of CL after the READ command is issued is captured into CORAL. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 272 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.2.2 Timing of read access to different row addresses MCLKO TRAS TRP MRAS TRCD TRCD MCAS MWE MA ROW COL ROW COL CL CL MD DATA DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRAS: RAS Active Time TRCD: RAS to CAS Delay Time CL: CAS Latency TRP: RAS Precharge Time *Timing when CL2 operating Fig. 10.20 Timing of Read Access to Different Row Addresses The above timing diagram shows that read access is made from CORAL to different row addresses of SDRAM. The first and next address to be read fall across an SDRAM page boundary, so the Pre-charge command is issued at the timing satisfying TRAS, and then after the elapse of TRP, the ACTV command is reissued, and then the READ command is issued. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 273 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.2.3 Timing of write access to same row address MCLKO MRAS TRCD MCAS MWE MA ROW COL COL COL COL MD DATA DATA DATA DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRCD: RAS to CAS Delay Time Fig. 10.21 Timing of Write Access to Same Row Address The above timing diagram shows that write access is made form times form CORAL to the same row address of SDRAM. The ACTV command is issued, and then after the elapse of TRCD, the WRITE command is issued to write to SDRAM. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 274 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.2.4 Timing of write access to different row addresses MCLKO TRAS TRP MRAS TRCD TRCD MCAS MWE MA ROW COL ROW COL MD DATA DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRAS: RAS Active Time TRCD: RAS to CAS Delay Time TRP: RAS Precharge Time Fig. 10.22 Timing of Write Access to Different Row Addresses The above timing diagram shows that write access is made from CORAL to different row addresses of SDRAM. The first and next address to be write fall across a SDRAM page boundary, so the n Pre-charge command is issued at the timing satisfying TRAS, and then after the elapse of TRP, the ACTV command is reissued, and then the WRITE command is issued. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 275 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.2.5 Timing of read/write access to same row address MCLKO MRAS TRCD MCAS MWE MA ROW COL COL CL LOWD MD DATA DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRAS: RAS Active Time TRCD: RAS to CAS Delay Time CL: CAS Latency TRP: RAS Precharge Time LOWD: Last Output to Write Command Delay Timing when CL2 operating Fig. 10.23 Timing of Read/Write Access to Same Row Address The above timing diagram shows that write access is made immediately after read access is made from CORAL to the same row address of SDRAM. Read data is output from SDRAM, LOWD elapses, and then the WRITE command is issued. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 276 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.2.6 Delay between ACTV commands MCLKO TRRD MRAS MCAS MWE MA ROW ROW ROW: Row Address TRRD: RAS to RAS Bank Active Delay Time Fig.10.24 Delay between ACTV Commands The ACTV command is issued from CORAL to the row address of SDRAM after the elapse of TRRD after issuance of the previous ACTV command. 12.2.7 Delay between Refresh command and next ACTV command MCLKO TRC MRAS MCAS MWE MA ROW ROW: Row Address TRC: RAS Cycle Time Fig. 10.25 Delay between Refresh Command and Next ACTV Command The ACTV command is issued after the elapse of TRC after issuance of the Refresh command. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 277 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.3 Display Timing 12.3.1 Non-interlace mode VTR+1 rasters VSP+1 rasters VDP+1 rasters Ri/Gi/Bi DISPE HSYNC VSYNC Assert Frame interrupt Assert VSYNC interrupt VSW+1 rasters Ri/Gi/Bi DISPE HSYNC Latency=14clocks HDP+1 clocks HSP+1 clocks HSW+1 clocks HTP+1 clocks DCLKO Ri/Gi/Bi DISPE 1 2 3 n-2 n-1 n = HDP+1 Fig. 10.26 Non-interlace Timing In the above diagram, VTR, HDP, etc., are the setting values of their associated registers. The VSYNC/frame interrupt is asserted when display of the last raster ends. When updating display parameters, synchronize with the frame interrupt so no display disturbance occurs. Calculation for the next frame is started immediately after the vertical synchronization pulse is asserted, so the parameters must be updated by the time that calculation is started. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 278 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.3.2 Interlace video mode VTR+1 rasters (odd field) VSP+1 rasters VDP+1 rasters Ri/Gi/Bi HSYNC VSYNC Assert Vsync Interrupt VSW+1 rasters Ri/Gi/Bi HSYNC VSYNC VDP+1 rasters VSP+1 rasters VSW+1 rasters VTR+1 rasters (even field) Assert Frame Interrupt Assert Vsync Interrupt Fig. 10.27 Interlace Video Timing In the above diagram, VTR, HDP, etc., are the setting values of their associated registers. The interlace mode also operates at the same timing as the interlace video mode. The only difference between the two modes is the output image data. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 279 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.3.3 Composite synchronous signal When the EEQ bit of the DCM register is "0", the CSYNC signal output waveform is as shown below. even field CSYNC VSYNC odd field odd field CSYNC VSYNC even field Fig 10.28 Composite Synchronous Signal without Equalizing Pulse When the EEQ bit of the DCM register is "1", the equalizing pulse is inserted into the CSYNC signal, producing the waveform shown below. even field CSYNC VSYNC odd field odd field CSYNC VSYNC even field Fig 10.29 Composite Synchronous Signal with Equalizing Pulse The equalizing pulse is inserted when the vertical blanking time period starts. It is also inserted three times after the vertical synchronization time period has elapsed. CAUTIONS 12.4 CPU Cautions MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 280 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 1) Enable the hardware wait for the areas to which CORAL is connected. When the normally not ready mode (RDY_MODE = 0) is used, set the software wait count to "1". When the normally ready mode (RDY_MODE = 1) is used, set the count to "2". When the normally ready mode is used (RDY_MODE = 1) and BS_MODE = L, set the software wait to 2. When the normally ready mode is enabled and BS_MODE = H, set the software wait to "3". 2) When starting DMA by issuing an external request, do so after setting the transfer count register (DTCR) and mode setting register (DSUR) of CORAL to the same value as the CPU setting. In the dual DMA without ACK mode or V832 mode, there is no need to set DTCR. 3) When CORAL is read-/write-accessed from the CPU during DMA transfer, do not access the registers and memories related to DMA transfer. If these registers and memories are accessed, reading and writing of the correct value is not assured. 4) Set DREQ (DMARQ) to "Low" level detection. 5) Set the DACK/DRACK of SH to high active output, DMAAK of V832 to high active, and XTC of V832 to low active. 12.5 SH3 Mode 1) When the XRDY pin is low, it is in the wait state. 2) DMA transfer in the single-address mode is not supported. 3) DMA transfer in the dual-address mode supports the direct address transfer mode, but does not support the indirect address transfer mode. 4) 16-byte DMA transfer in the dual-address mode is not supported. 5) The XINT signal asserts low active signal. 12.6 SH4 Mode 1) When the XRDY pin is low, it is in the ready state. 2) At DMA transfer in the single-address mode, transfer from the main memory (SH memory) to FIFO of CORAL can be performed, but transfer from CORAL to the main memory cannot be performed. 3) DMA transfer in the single-address mode is performed in units of 32 bits or 32 bytes. 4) SH4-mode 32-byte DMA transfer in the dual-address mode supports inter-memory transfer, but does not support transfer from memory to FIFO. 5) The XINT signal asserts low active signal. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 281 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 12.7 V832 Mode 1) When the XRDY pin is low, it is in the ready state. 2) Set the active level of DMAAK to high active in V832 mode. 3) DMA transfer supports the single transfer and demand transfer modes. 4) The XINT signal asserts high active signal. Set the V832-mode registers to high level trigger. 12.8 SPARClite 1) When the XRDY pin is low, it is in the ready state. 2) The SPARClite does not support the DMA transfer that issues the DREQ. 3) The XINT signal asserts low active signal. 12.9 Supported DMA Transfer Modes Single address mode SH3 Not supported Dual address mode Direct address transfer mode supported; indirect address transfer mode not supported. Transfer is performed in 32-bit units. Cycle steal mode and burst mode supported. SH4 Transfer performed in units of 32 bits or 32 bytes Cycle steal mode and burst mode supported Transfer is performed in 32-bit units. Transfer to memory is performed in 32-byte units. Transfer to FIFO not supported. Cycle steal mode and burst mode supported. Transfer is performed in 3 2-bit units. Single transfer mode and demand transfer mode supported. V832 SPARC lite MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 282 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13 ELECTRICAL CHARACTERISTICS Introduction 13.1 The values in this chapter are the final specification for CORAL-LB. 13.2 Maximum Rating Maximum Rating Parameter Power supply voltage Input voltage Output current Ambient for storage temperature Symbol VDDL VDDH VI IO TST *1 Maximum rating -0.5 < VDDL < 2.5 -0.5 < VDDH < 4.0 -0.5 < VI < VDDH+0.5 (<4.0) 13 -55 < TST < +125 Unit V V mA C *1 Includes PLL power supply MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 283 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.3 Recommended Operating Conditions 13.3.1 Recommended operating conditions Recommended Operating Conditions Parameter Symbol VDDL *1 VDDH AVD Input voltage (High level) Input voltage (low level) Input voltage to VREF VRO External resistance AOUT External resistance* 2 3 Rating Min. 1.65 3.0 2.7 2.0 -0.3 1.05 1.10 2.7 75 0.1 -40 85 Typ. 1.8 3.3 3.3 Max. 1.95 3.6 3.6 VDDH+0.3 0.8 1.15 Unit Supply voltage V VIH VIL VREF RREF RL CACOMP TA V V V K ohm ohm uF C ACOMP External capacitance* Ambient temperature for operation *1 *2 *3 Includes PLL power supply AOUTR, AOUTG, AOUTB pins ACOMPR, ACOMPG, ACOMPB pins 13.3.2 Note at power-on * There is no restriction on the sequence of power-on/power-off between VDDL and VDDH . However, do not apply only VDDH for more than a few seconds. * Do not input HSYNC, VSYNC, and EO signals when the power supply voltage is not applied. (See the input voltage item in Maximum rating.) * Immediately after power-on, input the "Low" level to the S pin for 500 ns or more. After the S pin is set to "High" level, input the "Low" level to the XRST pin for 300 s or more. And before the XRST pin is set to "High", please input the clock to the BCLKI pin for 10 clock or more. S XRST More than 500ns 300s MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 284 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.4 DC Characteristics 13.4.1 DC Characteristics Measuring condition: Parameter Output voltage ("High" level) Output voltage ("Low" level) Output current ("High" level) Output current ("Low" level) AOUT Output current*2 Full Scale*3 Zero Scale *2 VDDL = 1.8 1.5 V, VDDH = 3.3 0.3 V, VSS = 0.0 V, Ta = -40 to +85C Symbol Condition Rating Min. VDDH-0.2 Typ. Max. VDDH Unit VOH IOH=-100uA V VOL IOL=100uA 0.0 0.2 V -- VDDH=3.3V0.3V (*1) mA -- VDDH=3.3V0.3V (*1) mA IAOUT VREF=1.1V, RREF=2.7k ohm VREF=1.1V, 9.38 0 10.42 2 11.48 20 mA uA AOUT Output Voltage VAOUT RREF=2.7k ohm RL=75 ohm 0 0.7815 5 16 V Input leakage current Pin capacitance IL C A pF *1: Please refer "V-I characteristics diagram". L Type: Output characteristics of MD0-63, MDQM0-7 pins M Type: Output characteristics of pins other than signals indicated by L type and H type H Type: Output characteristics of XINT, DREQ, XRDY, MCLKO pins *2: AOUTR, AOUTG, AOUTB pin *3: Full Scale Output Current = (VREF/RREF) * 25.575 MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 285 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.4.2 V-I characteristics diagram Condition MAX: Process=Slow, Ta=85C, V DD=3.6V TYP: Process=Typical, Ta=25C, V DD=3.3V MIN: Process=Fast, Ta=-40C, V DD=3.0V Fig. V-I characteristics L, M type Condition MAX: Process=Slow, Ta=85C, V DD=3.6V TYP: Process=Typical, Ta=25C, V DD=3.3V MIN: Process=Fast, Ta=-40C, V DD=3.0V Fig. V-I characteristics H type MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 286 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.5 AC Characteristics 13.5.1 Host interface Clock Parameter BCLKI frequency BCLKI H-width BCLKI L-width Symbol fBCLKI tHBCLKI tLBCLKI 1 1 Condition Min. Rating Typ. Max. 100 Unit MHz ns ns Host interface signals (Operating condition: external load = 20 pF) Parameter Address set up time Address hold time XBS Set up time XBS Hold time XCS Set up time XCS Hold time XRD Set up time XRD Hold time XWE Set up time XWE Hold time Write data set up time Write data hold time DTACK Set up time DTACK Hold time DRACK Set up time DRACK Hold time Read data delay time (for XRD) Read data delay time XRDY Delay time (for XCS) XRDY Delay time XINT Delay time DREQ Delay time MODE Hold time Symbol tADS tADH tBSS tBSH tCSS tCSH tRDS tRDH tWES tWEH tWDS tWDH tDAKS tDAKH tDRKS tDRKH tRDDZ tRDD tRDYDZ tRDYD tINTD tDQRD tMODH *1 *2 Condition Rating Min. 3.0 0.0 3.0 0.0 3.0 0.0 3.0 0.0 5.5 0.0 3.5 0.0 3.0 0.0 3.0 0.0 4.5 4.5 3.5 2.5 3.0 3.5 10.5 9.5 7.0 6.0 7.0 7.0 20.0 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 Hold time required for canceling reset Valid data is output at assertion of XRDY and is retained until XRD is negated. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 287 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.5.2 Video interface Clock Parameter CLK Frequency CLK H-width CLK L-width DCLKI Frequency DCLKI H-width DCLKI L-width DCLKO frequency Symbol fCLK tHCLK tLCLK fDCLKI tHDCLKI tLDCLKI fDCLKO 5 5 67 25 25 67 Condition Rating Min. Typ. 14.318 Max. Unit MHz ns ns MHz ns ns MHz Input signals Parameter Symbol tWHSYNC0 tWHSYNC1 HSYNC Input setup time HSYNC Input hold time VSYNC Input pulse width tSHSYNC tHHSYNC tWHSYNC1 Condition *1 *2 *2 *2 Rating Min. 3 3 10 10 1 Typ. Max. Unit clock clock ns ns HSYNC 1 cycle HSYNC Input pulse width *1 *2 Applied only in PLL synchronization mode (CKS = 0), reference clock output from internal PLL (cycle = 1/14*fCLK) Applied only in DCLKI synchronization mode (CKS = 1), reference clock = DCLKI Output signals Parameter RGB Output delay time DISPE Output delay time HSYNC Output delay time VSYNC Output delay time CSYNC Output delay time GV Output delay time Symbol TRGB tDEO tDHSYNC tDVSYNC tDCSYNC tDGV Condition Rating Min. 2 2 2 2 2 2 Typ. Max. 10 10 10 10 10 10 Unit ns ns ns ns ns ns MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 288 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.5.3 Video Capture Interface Clock Parameter CCLK Frequency CCLKI H-width CCLKI L-width Symbol fCCLK tHCCLKI tLCCLKI 5 5 Condition Rating Min. Typ. 27 Max. Unit MHz ns ns Input signals Parameter VI setup time VI hold time Symbol tVIS tVIH Condition Rating Min. 11 2 Typ. Max. Unit ns ns MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 289 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.5.4 Graphics memory interface Condition: Clock frequency=133MHz, 100MHz, BCLK. Printed-wiring is isometry. An assumed external capacitance Parameter Min Board pattern SDRAM (CLK) SDRAM (D) SDRAM (A, DQM) 5.0 2.5 4.0 2.5 An assumed external capacitance Typ Max 15.0 4.0 6.5 5.0 Unit pF pF pF pF Clock Rating Min. Typ. Max. *1 1.0 1.0 *1 1.0 1.0 Parameter Symbol fMCLKO tHMCLKO tLMCLKO fMCLKI tHMCLKI tLMCLKI Condition Unit MHz ns ns MHz ns ns MCLKO Frequency MCLKO H-width MCLKO L-width MCLKI Frequency MCLKI H-width MCLKI L-width *1 For the bus-asynchronous mode, the frequency is 1/3 of the oscillation frequency of the internal PLL. For the bus-synchronous mode, the frequency is the same as the frequency of BCLKI. Input signals Parameter Symbol tMDIDS tMDIDH Condition *2 *2 Rating Min. 2.0 0.7 Typ. Max. Unit ns ns MD Input data setup time MD Input data hold time *2 It means against MCLKI. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 290 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL There are some cases regarding AC specifications of output signals. The following tables shows typical six cases of external SDRFAM capacitance. (1) External SDRAM capacitance case 1 External SDRAM capacitance SDRAM x1 MCLKO MA,MRAS,MCAS,MWE MD,DQM Total capacitance 9.9pF (DRAM CLK 2.5pF, Board pattern 5pF) 7.5pF (DRAM A.DQM 2.5pF, Board pattern 5pF) 9.0pF (DRAM D 4pF, Board pattern 5pF) Unit pF pF pF Output signals Parameter Symbol tDID tMAD tMDQMD tMDOD Condition Rating *1 Min. 0 1.0 1.1 1.1 Typ. Max. 4.2 5.0 5.4 5.4 Unit ns ns ns ns MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time MDQM Access time MD Output access time (2) External SDRAM capacitance case 2 External SDRAM capacitance SDRAM x1 MCLKO MA,MRAS,MCAS,MWE MD,DQM Total capacitance 25.4pF (DRAM CLK 4.0pF, Board pattern 15pF) 20.0pF (DRAM A.DQM 5pF, Board pattern 15pF) 21.5pF (DRAM D 6.5pF, Board pattern 15pF) Unit pF pF pF Output signals Parameter Symbol tDID tMAD tMDQMD tMDOD Condition Rating *1 Min. 0 1.0 1.2 1.2 Typ. Max. 3.5 5.2 5.5 5.5 Unit ns ns ns ns MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time MDQM Access time MD Output access time MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 291 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL (3) External SDRAM capacitance case 3 External SDRAM capacitance SDRAM x2 MCLKO MA,MRAS,MCAS,MWE MD,DQM Total capacitance 12.4pF (DRAM CLK 2.5pF x2, Board pattern 5pF) 10.0pF (DRAM A.DQM 2.5pF x2, Board pattern 5pF) 9.0pF (DRAM D 4pF, Board pattern 5pF) Unit pF pF pF Output signals Parameter Symbol tDID tMAD tMDQMD tMDOD Condition Rating *1 Min. 0 1.0 1.1 1.1 Typ. Max. 4.1 5.0 5.2 5.2 Unit ns ns ns ns MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time MDQM Access time MD Output access time (4) External SDRAM capacitance case 4 External SDRAM capacitance SDRAM x2 MCLKO MA,MRAS,MCAS,MWE MD,DQM Total capacitance 29.4pF (DRAM CLK 4.0pF x2, Board pattern 15pF) 25.0pF (DRAM A.DQM 5pF x2, Board pattern 15pF) 21.5pF (DRAM D 6.5pF, Board pattern 15pF) Unit pF pF pF Output signals Parameter Symbol tDID tMAD tMDQMD tMDOD Condition Rating *1 Min. 0 1.1 1.1 1.1 Typ. Max. 3.4 5.4 5.5 5.5 Unit ns ns ns ns MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time MDQM Access time MD Output access time MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 292 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL (5) External SDRAM capacitance case 5 External SDRAM capacitance SDRAM x4 MCLKO MA,MRAS,MCAS,MWE MD,DQM Total capacitance 17.4pF (DRAM CLK 2.5pF x4, Board pattern 5pF) 15.0pF (DRAM A.DQM 2.5pF x4, Board pattern 5pF) 9.0pF (DRAM D 4pF, Board pattern 5pF) Unit pF pF pF Output signals Parameter Symbol tDID tMAD tMDQMD tMDOD Condition Rating *1 Min. 0 1.0 1.0 1.0 Typ. Max. 3.9 5.2 5.0 5.0 Unit ns ns ns ns MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time MDQM Access time MD Output access time (6) External SDRAM capacitance case 6 External SDRAM capacitance SDRAM x4 MCLKO MA,MRAS,MCAS,MWE MD,DQM Total capacitance 37.3pF (DRAM CLK 4.0pF x4, Board pattern 15pF) 35.0pF (DRAM A.DQM 5pF x4, Board pattern 15pF) 21.5pF (DRAM D 6.5pF, Board pattern 15pF) Unit pF pF pF Output signals Parameter Symbol tDID tMAD tMDQMD tMDOD Condition Rating *1 Min. 0 1.2 1.0 1.0 Typ. Max. 3.4 5.7 5.3 5.3 Unit ns ns ns ns MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time MDQM Access time MD Output access time MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 293 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.5.5 PLL specifications Parameter Input frequency (typ.) Output frequency Duty ratio Jitter Rating 14.31818 MHz 400.9090 MHz 101.6 to 93.0% 60 to -60 ps x 28 H/L Pulse width ratio of PLL output Frequency tolerant of two consecutive clock cycles Description CLKSEL1 L L H L H L CLKSEL1 Input frequency 13.5 MHz 14.32 MHz 17.73 Hz Assured operation range (*1) 13.365 to 13.5 MHz 14.177 to 14.32 MHz 17.553 to 17.73 MHz *1 Assured operation input frequency range: Standard value -1% MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 294 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.6 AC Characteristics Measuring Conditions tr tf 80 % (VIH+V IL)/2 20 % 80 % 20 % Input tpHL tpLH Output V DD /2 V DD /2 tpZL tpLZ Output enabled V DD /2 0.5 V tpZH tpHZ 0.5 V V DD /2 Output disabled Tr, tf 5 ns VI H=2.0 V, VIL = 0.8V (3.3-V CMOS interface input) MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 295 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.7 Timing Diagram 13.7.1 Host interface Clock 1/f BCLKI t HBCLKI BCLKI t LBCLKI MODE hold time XRESET MODE tMODH XINT output delay times BCLK XINT tINT MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 296 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Host bus AC timing (Normally Not Ready) T1 BCLKI tADH A t BSH t BSS t BSH tADS Tsw1 Thw1 T2 t BSS XBS t CSH t CSS XCS tRDS tRDH XRD (RDXWR) t RDDZ Hi-Z tWES XWE (XMWE) tWDS tWDH t RDD t RDDZ Hi-Z D(output) Output data tWEH D(Input) t RDYDZ Hi-Z t RDYD t RDYD t RDYDZ Hi-Z XRDY t RDYDZ XWAIT Hi-Z t RDYD t RDYD tRDYDZ Hi-Z MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 297 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Host bus AC timing (Normally Ready) T1 BCLKI tADH A tBSH t BSS tADS Tsw1 Tsw2 Thw1 T2 tBSH tBSS XBS tCSH tCSS XCS t RDS tRDH XRD (RDXWR) t RDDZ D(output) Hi-Z tWES XWE (XMWE) tWDS tWDH tWEH tRDD tRDDZ Hi-Z Output data D(Input) tRDYDZ XRDY Hi-Z tRDYD tRDYDZ Hi-Z tRDYDZ XWAIT Hi-Z tRDYD t RDYD t RDYD tRDYDZ Hi-Z MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 298 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL DMA AC timing BCLKI tWDH D(Input) t DAKH t DAKS t DAKH t DAKS tWDS tWDH DTACK (XTC) t RRKH t DRKS t RRKH t DRKS DRACK (DMAAK ) tDRQD tDRQD DREQ *: The above timing diagram for the D pin is that of when a single DMA is used. When a dual DMA is used, see the host bus-timing diagram. MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 299 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.7.2 Video interface Clock 1/f CLK t HCLK CLK VIH VIL t LCLK HSYNC signal setup/hold 1/f DCLKI t HDCLKI DCLKI t LDCLKI HSYNC (input) t SHSYN t HHSYN Output signal delay DCLKO DR7-2, DG7-2 DB7-2 MD63-58* HSYNC (output) VSYNC (output) CSYNC, DE GV *Valid if XRGBEN = 0 tRGB , tDEO, tDHSYNC, tDVSYNC, tDCSYNC, tDGV MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 300 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.7.3 Video Capture Interface Clock 1/fCCLKI tHCCLKI CCLKI t LCCLKI Video input CCLKI VI t VIS tVIH MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 301 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL 13.7.4 Graphics memory interface Clock 1/f MCLKO, 1/f MCLKI tHMCLKO, tHMCLKI MCLKO, MCLKI tLMCLKO, tLMCLKI Input signal setup/hold time MCLKI MD Input data t MDIDS tMDIDH MCLKI signal delay MCLKO MCLKI t OID MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 302 FUJITSU LIMITED PRELIMINARY and CONFIDENTIAL Output signal delay MCLKO MA, MRAS, MCAS, MWE, MD, MDQM t MAD, tMDOD, tMDQMD MB86294/294S CORAL_LB Graphics Controller Specifications Rev. 1.0 303 FUJITSU SEMICONDUCTOR DATA SHEET BALL GRID ARRAY PACKAGE 256 PIN PLASTIC BGA-256P-M02 256-pin plastic BGA Lead pitch Pin matrix Sealing method 50 mil 20 Plastic mold (BGA-256P-M02) 256-pin plastic BGA (BGA-256P-M02) Note: The actual shape of corners may differ from the dimension. 27.000.20(1.06.008)SQ 24.000.10(.94.004) 2.300.20 (.091.008) 0.600.10 (.024.004) 24.130.20(.95.008) 1.270.20 (.05.008) 0.15(.006) INDEX O0.750.15(O.03.006) 1 PIN C 1995 FUJITSU LIMITED BGA256004SC-2-1 Dimensions in mm (inches). The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of the information or package dimensions in this document. 9711 FUJITSU SEMICONDUCTOR DATA SHEET QUAD FLAT PACKAGE 256 PIN PLASTIC FPT-256P-M09 256-pin plastic QFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight Remark 0.40 mm 28.0 x 28.0 mm Gullwing Plastic mold 4.03 mm MAX 5.74g Low heat resistance type P-FQFP256-28 x 28-0.40 (FPT-256P-M09) Code(Reference) 256-pin plastic QFP (FPT-256P-M09) 30.600.20(1.205.008)SQ 28.000.10(1.102.004)SQ 192 129 Pins width and pins thickness include plating thickness. 0.1450.055 (.006.002) 193 128 0.08(.003) Details of "A" part 3.730.30 (Mounting height) (.147.012) INDEX 0~8 256 65 0.40 -0.15 +0.10 +.004 .016 -.006 (Stand off) "A" LEAD No. 1 64 (0.50(.020)) M 0.25(.010) 0.40(.016) 0.180.05 (.007.002) 0.07(.003) 0.600.15 (.024.006) C 2000 FUJITSU LIMITED F256025S-c-2-3 Dimensions in mm (inches). The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of the information or package dimensions in this document. 0010 |
Price & Availability of MB86294
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |